diff options
author | Alexandre Courbot <acourbot@nvidia.com> | 2013-11-21 03:38:10 +0100 |
---|---|---|
committer | Peter De Schrijver <pdeschrijver@nvidia.com> | 2013-11-26 17:46:57 +0100 |
commit | 5ab5d4048e6ed8811245a4ea45264456c180545e (patch) | |
tree | 1c7b1a386a1d1137c4980858a79e7aa9de72a208 /drivers/clk/tegra/clk-tegra30.c | |
parent | clk: tegra: Properly setup PWM clock on Tegra30 (diff) | |
download | linux-5ab5d4048e6ed8811245a4ea45264456c180545e.tar.xz linux-5ab5d4048e6ed8811245a4ea45264456c180545e.zip |
clk: tegra: add FUSE clock device
This clock is needed to ensure the FUSE registers can be accessed
without freezing the system.
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Diffstat (limited to 'drivers/clk/tegra/clk-tegra30.c')
-rw-r--r-- | drivers/clk/tegra/clk-tegra30.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c index 3afa09761bb3..dcb6843b3a89 100644 --- a/drivers/clk/tegra/clk-tegra30.c +++ b/drivers/clk/tegra/clk-tegra30.c @@ -650,7 +650,7 @@ static struct tegra_devclk devclks[] __initdata = { { .con_id = "pcie", .dev_id = "tegra-pcie", .dt_id = TEGRA30_CLK_PCIE }, { .con_id = "afi", .dev_id = "tegra-pcie", .dt_id = TEGRA30_CLK_AFI }, { .con_id = "pciex", .dev_id = "tegra-pcie", .dt_id = TEGRA30_CLK_PCIEX }, - { .con_id = "fuse", .dev_id = "fuse-tegra", .dt_id = TEGRA30_CLK_FUSE }, + { .con_id = "fuse", .dt_id = TEGRA30_CLK_FUSE }, { .con_id = "fuse_burn", .dev_id = "fuse-tegra", .dt_id = TEGRA30_CLK_FUSE_BURN }, { .con_id = "apbif", .dev_id = "tegra30-ahub", .dt_id = TEGRA30_CLK_APBIF }, { .con_id = "hda2hdmi", .dev_id = "tegra30-hda", .dt_id = TEGRA30_CLK_HDA2HDMI }, |