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| author | Bill Huang <bilhuang@nvidia.com> | 2015-06-18 23:28:30 +0200 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2015-12-17 13:37:53 +0100 |
| commit | b5512b45d5ed699de328e17cd7c7027d89461920 (patch) | |
| tree | fbb0e8547493c65828b45fa0d80df76ee1669517 /drivers/clk/tegra/clk.h | |
| parent | clk: tegra: pll: Add support for PLLMB for Tegra210 (diff) | |
| download | linux-b5512b45d5ed699de328e17cd7c7027d89461920.tar.xz linux-b5512b45d5ed699de328e17cd7c7027d89461920.zip | |
clk: tegra: pll: Adjust vco_min if SDM present
This code makes use of the SDM fractional divider if present to
constrain the allowable programming range of the PLL divider register
bitfields to take advantage of higher frequency granularity that can
be induced by the SDM divider.
Based on original work by Aleksandr Frid <afrid@nvidia.com>
Signed-off-by: Bill Huang <bilhuang@nvidia.com>
Signed-off-by: Rhyland Klein <rklein@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to '')
| -rw-r--r-- | drivers/clk/tegra/clk.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h index 8724dc245f68..f94b1789c333 100644 --- a/drivers/clk/tegra/clk.h +++ b/drivers/clk/tegra/clk.h @@ -202,6 +202,8 @@ struct div_nmp { * PLL's based on fractional divider value. * @calc_rate: Callback used to change how out of table * rates (dividers and multipler) are calculated. + * @adjust_vco: Callback to adjust the programming range of the + * divider range (if SDM is present) * * Flags: * TEGRA_PLL_USE_LOCK - This flag indicated to use lock bits for @@ -269,6 +271,8 @@ struct tegra_clk_pll_params { int (*calc_rate)(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg, unsigned long rate, unsigned long parent_rate); + unsigned long (*adjust_vco)(struct tegra_clk_pll_params *pll_params, + unsigned long parent_rate); }; #define TEGRA_PLL_USE_LOCK BIT(0) |