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| author | Rhyland Klein <rklein@nvidia.com> | 2016-03-21 20:58:52 +0100 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2016-04-28 12:41:50 +0200 |
| commit | 926655f929063619b13db8b4f2ef8c9a08605492 (patch) | |
| tree | ffcb529ae83a81e7840b9f57ccf11006fb15fd56 /drivers/clk/tegra/clk.h | |
| parent | clk: tegra: Add sor_safe clock (diff) | |
| download | linux-926655f929063619b13db8b4f2ef8c9a08605492.tar.xz linux-926655f929063619b13db8b4f2ef8c9a08605492.zip | |
clk: tegra: Fix pllre Tegra210 and add pll_re_out1
Use a new Tegra210 version of the pll_register_pllre function to
allow setting the proper settings for the m and n div fields.
Additionally define PLL_RE_OUT1 on Tegra210.
Signed-off-by: Rhyland Klein <rklein@nvidia.com>
[treding@nvidia.com: define PLLRE_OUT1 register offset]
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'drivers/clk/tegra/clk.h')
| -rw-r--r-- | drivers/clk/tegra/clk.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h index 7264f17e269e..9421f0310999 100644 --- a/drivers/clk/tegra/clk.h +++ b/drivers/clk/tegra/clk.h @@ -386,6 +386,12 @@ struct clk *tegra_clk_register_pllre(const char *name, const char *parent_name, struct tegra_clk_pll_params *pll_params, spinlock_t *lock, unsigned long parent_rate); +struct clk *tegra_clk_register_pllre_tegra210(const char *name, + const char *parent_name, void __iomem *clk_base, + void __iomem *pmc, unsigned long flags, + struct tegra_clk_pll_params *pll_params, + spinlock_t *lock, unsigned long parent_rate); + struct clk *tegra_clk_register_plle_tegra114(const char *name, const char *parent_name, void __iomem *clk_base, unsigned long flags, |