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| author | Bill Huang <bilhuang@nvidia.com> | 2015-06-18 23:28:35 +0200 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2015-12-17 13:37:55 +0100 |
| commit | 139fd30943c3c8ed76d0ce08ff711cfff3b118ec (patch) | |
| tree | e5d3d9bec2145062c1ad25c44f50d21ab95737bb /drivers/clk/tegra/clk.h | |
| parent | clk: tegra: pll: Add logic for SS (diff) | |
| download | linux-139fd30943c3c8ed76d0ce08ff711cfff3b118ec.tar.xz linux-139fd30943c3c8ed76d0ce08ff711cfff3b118ec.zip | |
clk: tegra: Add Super Gen5 Logic
Super clock divider control and clock source mux of Tegra210 has changed
a little against prior SoCs, this patch adds Gen5 logic to address those
differences.
Signed-off-by: Bill Huang <bilhuang@nvidia.com>
Signed-off-by: Rhyland Klein <rklein@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'drivers/clk/tegra/clk.h')
| -rw-r--r-- | drivers/clk/tegra/clk.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h index 4883507c59dc..cb9670ee22a6 100644 --- a/drivers/clk/tegra/clk.h +++ b/drivers/clk/tegra/clk.h @@ -740,6 +740,9 @@ int tegra_osc_clk_init(void __iomem *clk_base, struct tegra_clk *clks, void tegra_super_clk_gen4_init(void __iomem *clk_base, void __iomem *pmc_base, struct tegra_clk *tegra_clks, struct tegra_clk_pll_params *pll_params); +void tegra_super_clk_gen5_init(void __iomem *clk_base, + void __iomem *pmc_base, struct tegra_clk *tegra_clks, + struct tegra_clk_pll_params *pll_params); #ifdef CONFIG_TEGRA_CLK_EMC struct clk *tegra_clk_register_emc(void __iomem *base, struct device_node *np, |