diff options
| author | Dmitry Osipenko <digetx@gmail.com> | 2018-05-08 18:26:05 +0200 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2018-05-18 12:35:07 +0200 |
| commit | efc351b1f46f55ba3f9fa83c490c55243c3a676b (patch) | |
| tree | 621b706c8b45dd7c5aad6af59ebc50ab3539b8bb /drivers/clk/tegra | |
| parent | clk: tegra20: Add DEV1/DEV2 OSC dividers (diff) | |
| download | linux-efc351b1f46f55ba3f9fa83c490c55243c3a676b.tar.xz linux-efc351b1f46f55ba3f9fa83c490c55243c3a676b.zip | |
clk: tegra20: Correct parents of CDEV1/2 clocks
Parents of CDEV1/2 clocks are determined by muxing of the corresponding
pins. Pinctrl driver now provides the CDEV1/2 clock muxes and hence
CDEV1/2 clocks could have correct parents. Set CDEV1/2 parents to the
corresponding muxes to fix the parents.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Reviewed-by: Marcel Ziswiler <marcel@ziswiler.com>
Tested-by: Marcel Ziswiler <marcel@ziswiler.com>
Tested-by: Marc Dietrich <marvin24@gmx.de>
Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'drivers/clk/tegra')
| -rw-r--r-- | drivers/clk/tegra/clk-tegra20.c | 6 |
1 files changed, 2 insertions, 4 deletions
diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c index ad5a7b5e3a39..636500a98561 100644 --- a/drivers/clk/tegra/clk-tegra20.c +++ b/drivers/clk/tegra/clk-tegra20.c @@ -846,14 +846,12 @@ static void __init tegra20_periph_clk_init(void) NULL); /* cdev1 */ - clk = clk_register_fixed_rate(NULL, "cdev1_fixed", NULL, 0, 26000000); - clk = tegra_clk_register_periph_gate("cdev1", "cdev1_fixed", 0, + clk = tegra_clk_register_periph_gate("cdev1", "cdev1_mux", 0, clk_base, 0, 94, periph_clk_enb_refcnt); clks[TEGRA20_CLK_CDEV1] = clk; /* cdev2 */ - clk = clk_register_fixed_rate(NULL, "cdev2_fixed", NULL, 0, 26000000); - clk = tegra_clk_register_periph_gate("cdev2", "cdev2_fixed", 0, + clk = tegra_clk_register_periph_gate("cdev2", "cdev2_mux", 0, clk_base, 0, 93, periph_clk_enb_refcnt); clks[TEGRA20_CLK_CDEV2] = clk; |