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authorAndrew Bresticker <abrestic@chromium.org>2013-12-27 01:44:27 +0100
committerPeter De Schrijver <pdeschrijver@nvidia.com>2014-02-17 15:18:34 +0100
commit3de5bdfb4cb3bd99052a4ffaee358189779be042 (patch)
tree0ca23dade9b01c0f5ff3c1d6101e1533f401e5fa /drivers/clk/tegra
parentclk: tegra: cclk_lp has a pllx/2 divider (diff)
downloadlinux-3de5bdfb4cb3bd99052a4ffaee358189779be042.tar.xz
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clk: tegra: use max divider if divider overflows
When requesting a rate less than the minimum clock rate for a divider, use the maximum divider value instead of bailing out with an error. This matches the behavior of the generic clock divider. Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Diffstat (limited to 'drivers/clk/tegra')
-rw-r--r--drivers/clk/tegra/clk-divider.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/tegra/clk-divider.c b/drivers/clk/tegra/clk-divider.c
index 4d75b1f37e3a..290f9c1a3749 100644
--- a/drivers/clk/tegra/clk-divider.c
+++ b/drivers/clk/tegra/clk-divider.c
@@ -59,7 +59,7 @@ static int get_div(struct tegra_clk_frac_div *divider, unsigned long rate,
return 0;
if (divider_ux1 > get_max_div(divider))
- return -EINVAL;
+ return get_max_div(divider);
return divider_ux1;
}