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authorJim Lin <jilin@nvidia.com>2014-05-15 02:32:58 +0200
committerMike Turquette <mturquette@linaro.org>2014-05-23 07:14:52 +0200
commit9d61707b1f83324fc30918787cb6ef101997ecbd (patch)
tree4ab9ab1d7bdda71429326171c8392a6b27df4b34 /drivers/clk/tegra
parentclk: tegra: Enable hardware control of PLLE (diff)
downloadlinux-9d61707b1f83324fc30918787cb6ef101997ecbd.tar.xz
linux-9d61707b1f83324fc30918787cb6ef101997ecbd.zip
clk: tegra: Fix xusb_fs_src mux
The parent-to-index mapping for xusb_fs_src is incorrect. Fix it by adding a mux table. Signed-off-by: Jim Lin <jilin@nvidia.com> Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
Diffstat (limited to 'drivers/clk/tegra')
-rw-r--r--drivers/clk/tegra/clk-tegra-periph.c4
1 files changed, 3 insertions, 1 deletions
diff --git a/drivers/clk/tegra/clk-tegra-periph.c b/drivers/clk/tegra/clk-tegra-periph.c
index 1fa5c3f33b20..a4063bc25208 100644
--- a/drivers/clk/tegra/clk-tegra-periph.c
+++ b/drivers/clk/tegra/clk-tegra-periph.c
@@ -329,7 +329,9 @@ static u32 mux_clkm_pllp_pllc_pllre_idx[] = {
static const char *mux_clkm_48M_pllp_480M[] = {
"clk_m", "pll_u_48M", "pll_p", "pll_u_480M"
};
-#define mux_clkm_48M_pllp_480M_idx NULL
+static u32 mux_clkm_48M_pllp_480M_idx[] = {
+ [0] = 0, [1] = 2, [2] = 4, [3] = 6,
+};
static const char *mux_clkm_pllre_clk32_480M_pllc_ref[] = {
"clk_m", "pll_re_out", "clk_32k", "pll_u_480M", "pll_c", "pll_ref"