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| author | Bill Huang <bilhuang@nvidia.com> | 2015-06-18 23:28:22 +0200 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2015-11-20 18:04:49 +0100 |
| commit | 56fd27b31f1a216623f285bb77b4bcb6129e84c2 (patch) | |
| tree | 8bad50beb11b3a32a70a853e23c9203311b333cf /drivers/clk/tegra | |
| parent | clk: tegra: pll: Update warning message (diff) | |
| download | linux-56fd27b31f1a216623f285bb77b4bcb6129e84c2.tar.xz linux-56fd27b31f1a216623f285bb77b4bcb6129e84c2.zip | |
clk: tegra: pll: Change misc_reg count from 3 to 6
New SoC's may have more than 3 MISC registers, so bump up the array size
and use a #define to be more informative about the value.
Reviewed-by: Benson Leung <bleung@chromium.org>
Signed-off-by: Bill Huang <bilhuang@nvidia.com>
Signed-off-by: Rhyland Klein <rklein@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'drivers/clk/tegra')
| -rw-r--r-- | drivers/clk/tegra/clk.h | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h index ced19e7c68d2..488ee677e15b 100644 --- a/drivers/clk/tegra/clk.h +++ b/drivers/clk/tegra/clk.h @@ -156,6 +156,8 @@ struct div_nmp { u8 override_divp_shift; }; +#define MAX_PLL_MISC_REG_COUNT 6 + /** * struct tegra_clk_pll_params - PLL parameters * @@ -225,7 +227,7 @@ struct tegra_clk_pll_params { u32 iddq_bit_idx; u32 aux_reg; u32 dyn_ramp_reg; - u32 ext_misc_reg[3]; + u32 ext_misc_reg[MAX_PLL_MISC_REG_COUNT]; u32 pmc_divnm_reg; u32 pmc_divp_reg; u32 flags; |