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| author | Lee Jones <lee.jones@linaro.org> | 2021-01-26 13:45:21 +0100 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2021-02-11 04:42:41 +0100 |
| commit | ed1b7dd7021ba0c3b1acba766542cb206be05074 (patch) | |
| tree | 078be0bae2994abed462ac4c26a70595e8c23fe2 /drivers/clk/ti/clkt_dpll.c | |
| parent | clk: zynq: pll: Fix kernel-doc formatting in 'clk_register_zynq_pll's header (diff) | |
| download | linux-ed1b7dd7021ba0c3b1acba766542cb206be05074.tar.xz linux-ed1b7dd7021ba0c3b1acba766542cb206be05074.zip | |
clk: ti: clkt_dpll: Fix some kernel-doc misdemeanours
Fixes the following W=1 kernel build warning(s):
drivers/clk/ti/clkt_dpll.c:284: warning: Function parameter or member 'hw' not described in 'omap2_dpll_round_rate'
drivers/clk/ti/clkt_dpll.c:284: warning: Function parameter or member 'parent_rate' not described in 'omap2_dpll_round_rate'
drivers/clk/ti/clkt_dpll.c:284: warning: Excess function parameter 'clk' description in 'omap2_dpll_round_rate'
Cc: Tero Kristo <kristo@kernel.org>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: Richard Woodruff <r-woodruff2@ti.com>
Cc: linux-omap@vger.kernel.org
Cc: linux-clk@vger.kernel.org
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Link: https://lore.kernel.org/r/20210126124540.3320214-3-lee.jones@linaro.org
Reviewed-by: Tero Kristo <kristo@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to '')
| -rw-r--r-- | drivers/clk/ti/clkt_dpll.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/clk/ti/clkt_dpll.c b/drivers/clk/ti/clkt_dpll.c index 87ece6cd4226..dfaa4d1f0b64 100644 --- a/drivers/clk/ti/clkt_dpll.c +++ b/drivers/clk/ti/clkt_dpll.c @@ -269,8 +269,9 @@ unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk) /** * omap2_dpll_round_rate - round a target rate for an OMAP DPLL - * @clk: struct clk * for a DPLL + * @hw: struct clk_hw containing the struct clk * for a DPLL * @target_rate: desired DPLL clock rate + * @parent_rate: parent's DPLL clock rate * * Given a DPLL and a desired target rate, round the target rate to a * possible, programmable rate for this DPLL. Attempts to select the |