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| author | Michael Turquette <mturquette@linaro.org> | 2015-01-28 01:33:45 +0100 |
|---|---|---|
| committer | Michael Turquette <mturquette@linaro.org> | 2015-01-28 01:33:45 +0100 |
| commit | 8f101aa0272c21b116fd2b53c4ff7815698e4814 (patch) | |
| tree | 2e20c4751888aee4f10745fbf41939fbbc161a36 /drivers/clk/zynq/pll.c | |
| parent | Merge tag 'v3.20-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/... (diff) | |
| parent | sunxi: clk: Set sun6i-pll1 n_start = 1 (diff) | |
| download | linux-8f101aa0272c21b116fd2b53c4ff7815698e4814.tar.xz linux-8f101aa0272c21b116fd2b53c4ff7815698e4814.zip | |
Merge tag 'sunxi-clocks-for-3.20' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux into clk-next
Allwinner clock changes for 3.20
The set of clock changes for the 3.20 merge window, with mostly:
- Some PLL fixes for the A80 and A31
- The MMC custom phase functions are removed, and moved over to the generic
phase API.
- Add the A80 MMC clocks
Some DT changes slipped here as well, to preserve bisectability.
Diffstat (limited to 'drivers/clk/zynq/pll.c')
0 files changed, 0 insertions, 0 deletions