diff options
| author | Boris BREZILLON <boris.brezillon@free-electrons.com> | 2014-09-02 09:50:17 +0200 |
|---|---|---|
| committer | Mike Turquette <mturquette@linaro.org> | 2014-09-03 00:37:22 +0200 |
| commit | 13a6073d4c5db3103011eebe8c68b049323ced20 (patch) | |
| tree | a9e2dee2d3c352d77e7275b28d853eca06fb13ab /drivers/clk/zynq | |
| parent | clk: at91: fix recalc_rate implementation of PLL driver (diff) | |
| download | linux-13a6073d4c5db3103011eebe8c68b049323ced20.tar.xz linux-13a6073d4c5db3103011eebe8c68b049323ced20.zip | |
clk: at91: rework rm9200 USB clock to propagate set_rate to the parent clk
The RM9200 USB clock is actually connected to a single parent (the PLLB)
on which we can apply a specific divider.
The USB clock divider does not allow for fine grained control on the USB
clock frequency, hence propagating the set_rate request to the parent is
the only choice we have to properly configure the USB clock rate.
Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
Reported-by: Gaël PORTAY <gael.portay@gmail.com>
Tested-by: Gaël PORTAY <gael.portay@gmail.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Diffstat (limited to 'drivers/clk/zynq')
0 files changed, 0 insertions, 0 deletions