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| author | Jolly Shah <jolly.shah@xilinx.com> | 2018-10-08 20:21:46 +0200 |
|---|---|---|
| committer | Michal Simek <michal.simek@xilinx.com> | 2018-10-09 13:29:19 +0200 |
| commit | 3fde0e16d016ecb273f0fa404b5d56b947fc0576 (patch) | |
| tree | 570fc7609976fd1f275725bf63530bf177511dd8 /drivers/clk/zynqmp/Makefile | |
| parent | dt-bindings: clock: Add bindings for ZynqMP clock driver (diff) | |
| download | linux-3fde0e16d016ecb273f0fa404b5d56b947fc0576.tar.xz linux-3fde0e16d016ecb273f0fa404b5d56b947fc0576.zip | |
drivers: clk: Add ZynqMP clock driver
This patch adds CCF compliant clock driver for ZynqMP.
Clock driver queries supported clock information from
firmware and regiters pll and output clocks with CCF.
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Signed-off-by: Tejas Patel <tejasp@xilinx.com>
Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Acked-by: Olof Johansson <olof@lixom.net>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Diffstat (limited to 'drivers/clk/zynqmp/Makefile')
| -rw-r--r-- | drivers/clk/zynqmp/Makefile | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/clk/zynqmp/Makefile b/drivers/clk/zynqmp/Makefile new file mode 100644 index 000000000000..0ec24bfe0f18 --- /dev/null +++ b/drivers/clk/zynqmp/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0 +# Zynq Ultrascale+ MPSoC clock specific Makefile + +obj-$(CONFIG_ARCH_ZYNQMP) += pll.o clk-gate-zynqmp.o divider.o clk-mux-zynqmp.o clkc.o |