diff options
| author | Chen-Yu Tsai <wens@csie.org> | 2014-02-03 02:51:37 +0100 |
|---|---|---|
| committer | Emilio López <emilio@elopez.com.ar> | 2014-02-03 04:24:32 +0100 |
| commit | f64111ebaf6776558f0e60d0ea8c7a9c579b9436 (patch) | |
| tree | 9872cf508b43a63a9e93de59e6667a4c09f24e16 /drivers/clk | |
| parent | Linus 3.14-rc1 (diff) | |
| download | linux-f64111ebaf6776558f0e60d0ea8c7a9c579b9436.tar.xz linux-f64111ebaf6776558f0e60d0ea8c7a9c579b9436.zip | |
clk: sunxi: add clock-output-names dt property support
sunxi clock drivers use dt node name as clock name, but clock
nodes should be named clk@X, so the names would be the same.
Let the drivers read clock names from dt clock-output-names
property.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Emilio López <emilio@elopez.com.ar>
Diffstat (limited to 'drivers/clk')
| -rw-r--r-- | drivers/clk/sunxi/clk-sunxi.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c index abb6c5ac8a10..0ed97946c457 100644 --- a/drivers/clk/sunxi/clk-sunxi.c +++ b/drivers/clk/sunxi/clk-sunxi.c @@ -51,6 +51,8 @@ static void __init sun4i_osc_clk_setup(struct device_node *node) if (!gate) goto err_free_fixed; + of_property_read_string(node, "clock-output-names", &clk_name); + /* set up gate and fixed rate properties */ gate->reg = of_iomap(node, 0); gate->bit_idx = SUNXI_OSC24M_GATE; @@ -601,6 +603,8 @@ static void __init sunxi_mux_clk_setup(struct device_node *node, (parents[i] = of_clk_get_parent_name(node, i)) != NULL) i++; + of_property_read_string(node, "clock-output-names", &clk_name); + clk = clk_register_mux(NULL, clk_name, parents, i, CLK_SET_RATE_NO_REPARENT, reg, data->shift, SUNXI_MUX_GATE_WIDTH, @@ -660,6 +664,8 @@ static void __init sunxi_divider_clk_setup(struct device_node *node, clk_parent = of_clk_get_parent_name(node, 0); + of_property_read_string(node, "clock-output-names", &clk_name); + clk = clk_register_divider(NULL, clk_name, clk_parent, 0, reg, data->shift, data->width, data->pow ? CLK_DIVIDER_POWER_OF_TWO : 0, |