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authorTero Kristo <t-kristo@ti.com>2016-03-16 20:54:55 +0100
committerStephen Boyd <sboyd@codeaurora.org>2016-04-16 02:26:18 +0200
commitc5cc2a0bc930f1ae00b198aeb752acc3bdd4d5a7 (patch)
tree3ea618128d355ba5553f2af10e8eb8ad6555b4d0 /drivers/clk
parentclk: tango4: improve clkgen driver (diff)
downloadlinux-c5cc2a0bc930f1ae00b198aeb752acc3bdd4d5a7.tar.xz
linux-c5cc2a0bc930f1ae00b198aeb752acc3bdd4d5a7.zip
clk: ti: dpll: add support for specifying max rate for DPLLs
DPLLs typically have a maximum rate they can support, and this varies from DPLL to DPLL. Add support of the maximum rate value to the DPLL data struct, and also add check for this in the DPLL round_rate function. Signed-off-by: Tero Kristo <t-kristo@ti.com> Reviewed-by: Nishanth Menon <nm@ti.com> Cc: Tomi Valkeinen <tomi.valkeinen@ti.com> Cc: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Diffstat (limited to 'drivers/clk')
-rw-r--r--drivers/clk/ti/clkt_dpll.c3
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/clk/ti/clkt_dpll.c b/drivers/clk/ti/clkt_dpll.c
index 032c658a5f5e..b919fdfe8256 100644
--- a/drivers/clk/ti/clkt_dpll.c
+++ b/drivers/clk/ti/clkt_dpll.c
@@ -301,6 +301,9 @@ long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate,
dd = clk->dpll_data;
+ if (dd->max_rate && target_rate > dd->max_rate)
+ target_rate = dd->max_rate;
+
ref_rate = clk_hw_get_rate(dd->clk_ref);
clk_name = clk_hw_get_name(hw);
pr_debug("clock: %s: starting DPLL round_rate, target rate %lu\n",