diff options
| author | Paul Cercueil <paul@crapouillou.net> | 2018-01-16 16:47:53 +0100 |
|---|---|---|
| committer | James Hogan <jhogan@kernel.org> | 2018-01-18 23:05:13 +0100 |
| commit | 268db077ac47d3b5d8e3a768bf9dc5cb32ce6074 (patch) | |
| tree | 59380382f525ff4869a1ac1d5b586fde3059ea48 /drivers/clk | |
| parent | clk: ingenic: Fix recalc_rate for clocks with fixed divider (diff) | |
| download | linux-268db077ac47d3b5d8e3a768bf9dc5cb32ce6074.tar.xz linux-268db077ac47d3b5d8e3a768bf9dc5cb32ce6074.zip | |
clk: ingenic: support PLLs with no bypass bit
The second PLL of the JZ4770 does not have a bypass bit.
This commit makes it possible to support it with the current common CGU
code.
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Maarten ter Huurne <maarten@treewalker.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/18479/
Signed-off-by: James Hogan <jhogan@kernel.org>
Diffstat (limited to 'drivers/clk')
| -rw-r--r-- | drivers/clk/ingenic/cgu.c | 3 | ||||
| -rw-r--r-- | drivers/clk/ingenic/cgu.h | 2 |
2 files changed, 4 insertions, 1 deletions
diff --git a/drivers/clk/ingenic/cgu.c b/drivers/clk/ingenic/cgu.c index a2e73a6d60fd..381c4a17a1fc 100644 --- a/drivers/clk/ingenic/cgu.c +++ b/drivers/clk/ingenic/cgu.c @@ -100,7 +100,8 @@ ingenic_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) n += pll_info->n_offset; od_enc = ctl >> pll_info->od_shift; od_enc &= GENMASK(pll_info->od_bits - 1, 0); - bypass = !!(ctl & BIT(pll_info->bypass_bit)); + bypass = !pll_info->no_bypass_bit && + !!(ctl & BIT(pll_info->bypass_bit)); enable = !!(ctl & BIT(pll_info->enable_bit)); if (bypass) diff --git a/drivers/clk/ingenic/cgu.h b/drivers/clk/ingenic/cgu.h index f1527cf75b3f..9da34910bd80 100644 --- a/drivers/clk/ingenic/cgu.h +++ b/drivers/clk/ingenic/cgu.h @@ -48,6 +48,7 @@ * @bypass_bit: the index of the bypass bit in the PLL control register * @enable_bit: the index of the enable bit in the PLL control register * @stable_bit: the index of the stable bit in the PLL control register + * @no_bypass_bit: if set, the PLL has no bypass functionality */ struct ingenic_cgu_pll_info { unsigned reg; @@ -58,6 +59,7 @@ struct ingenic_cgu_pll_info { u8 bypass_bit; u8 enable_bit; u8 stable_bit; + bool no_bypass_bit; }; /** |