diff options
| author | Gabe Black <gabeblack@chromium.org> | 2013-12-27 01:44:21 +0100 |
|---|---|---|
| committer | Peter De Schrijver <pdeschrijver@nvidia.com> | 2014-02-17 15:18:02 +0100 |
| commit | 2ec35fd503bf6367ba55ed94dcb68edfe0d26e6a (patch) | |
| tree | 80532460e0a1598b4382f2e7a42287c075f758c7 /drivers/clk | |
| parent | clk: tegra: Correct clock number for UARTE (diff) | |
| download | linux-2ec35fd503bf6367ba55ed94dcb68edfe0d26e6a.tar.xz linux-2ec35fd503bf6367ba55ed94dcb68edfe0d26e6a.zip | |
clk: tegra: Fix PLLP rate table
This table had settings for 216MHz, but PLLP is (and is supposed to be)
configured at 408MHz. If that table is used and PLLP_BASE_OVRRIDE is
not set, the kernel will panic in clk_pll_recalc_rate().
Signed-off-by: Gabe Black <gabeblack@google.com>
Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Diffstat (limited to 'drivers/clk')
| -rw-r--r-- | drivers/clk/tegra/clk-tegra124.c | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/drivers/clk/tegra/clk-tegra124.c b/drivers/clk/tegra/clk-tegra124.c index aff86b5bc745..28bb238d9807 100644 --- a/drivers/clk/tegra/clk-tegra124.c +++ b/drivers/clk/tegra/clk-tegra124.c @@ -516,11 +516,11 @@ static struct div_nmp pllp_nmp = { }; static struct tegra_clk_pll_freq_table pll_p_freq_table[] = { - {12000000, 216000000, 432, 12, 1, 8}, - {13000000, 216000000, 432, 13, 1, 8}, - {16800000, 216000000, 360, 14, 1, 8}, - {19200000, 216000000, 360, 16, 1, 8}, - {26000000, 216000000, 432, 26, 1, 8}, + {12000000, 408000000, 408, 12, 0, 8}, + {13000000, 408000000, 408, 13, 0, 8}, + {16800000, 408000000, 340, 14, 0, 8}, + {19200000, 408000000, 340, 16, 0, 8}, + {26000000, 408000000, 408, 26, 0, 8}, {0, 0, 0, 0, 0, 0}, }; |