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authorAtish Patra <atish.patra@wdc.com>2019-03-22 22:54:11 +0100
committerThomas Gleixner <tglx@linutronix.de>2019-03-23 12:25:34 +0100
commit32d0be018f6f5ee2d5d19c4795304613560814cf (patch)
treea473db7707902cb56ea5a8ffb05a8d2e5055656c /drivers/clocksource/clps711x-timer.c
parentclocksource/drivers/mips-gic-timer: Make gic_compare_irqaction static (diff)
downloadlinux-32d0be018f6f5ee2d5d19c4795304613560814cf.tar.xz
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clocksource/drivers/riscv: Fix clocksource mask
For all riscv architectures (RV32, RV64 and RV128), the clocksource is a 64 bit incrementing counter. Fix the clock source mask accordingly. Tested on both 64bit and 32 bit virt machine in QEMU. Fixes: 62b019436814 ("clocksource: new RISC-V SBI timer driver") Signed-off-by: Atish Patra <atish.patra@wdc.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Anup Patel <anup@brainfault.org> Cc: Albert Ou <aou@eecs.berkeley.edu> Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Cc: linux-riscv@lists.infradead.org Cc: Palmer Dabbelt <palmer@sifive.com> Cc: Anup Patel <Anup.Patel@wdc.com> Cc: Damien Le Moal <Damien.LeMoal@wdc.com> Cc: stable@vger.kernel.org Link: https://lkml.kernel.org/r/20190322215411.19362-1-atish.patra@wdc.com
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