diff options
| author | Dmitry Osipenko <digetx@gmail.com> | 2019-06-18 16:03:55 +0200 |
|---|---|---|
| committer | Daniel Lezcano <daniel.lezcano@linaro.org> | 2019-06-25 19:49:18 +0200 |
| commit | 2e08a4bb96fd275d42711af10b3484164046bd1d (patch) | |
| tree | 1cb710f994cd6f934b6ed6163fa16a243a761c2e /drivers/clocksource/timer-tegra.c | |
| parent | clocksource/drivers/tegra: Drop unneeded typecasting in one place (diff) | |
| download | linux-2e08a4bb96fd275d42711af10b3484164046bd1d.tar.xz linux-2e08a4bb96fd275d42711af10b3484164046bd1d.zip | |
clocksource/drivers/tegra: Add verbose definition for 1MHz constant
Convert all 1MHz literals to a verbose constant for better readability.
Suggested-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Diffstat (limited to 'drivers/clocksource/timer-tegra.c')
| -rw-r--r-- | drivers/clocksource/timer-tegra.c | 12 |
1 files changed, 7 insertions, 5 deletions
diff --git a/drivers/clocksource/timer-tegra.c b/drivers/clocksource/timer-tegra.c index f7a09d88dacb..cc90f22c559b 100644 --- a/drivers/clocksource/timer-tegra.c +++ b/drivers/clocksource/timer-tegra.c @@ -46,6 +46,8 @@ #define TIMER1_IRQ_IDX 0 #define TIMER10_IRQ_IDX 10 +#define TIMER_1MHz 1000000 + static u32 usec_config; static void __iomem *timer_reg_base; @@ -160,7 +162,7 @@ static unsigned long tegra_delay_timer_read_counter_long(void) static struct delay_timer tegra_delay_timer = { .read_current_timer = tegra_delay_timer_read_counter_long, - .freq = 1000000, + .freq = TIMER_1MHz, }; #endif @@ -226,7 +228,7 @@ static inline unsigned long tegra_rate_for_timer(struct timer_of *to, * parent clock. */ if (tegra20) - return 1000000; + return TIMER_1MHz; return timer_of_rate(to); } @@ -315,11 +317,11 @@ static int __init tegra_init_timer(struct device_node *np, bool tegra20, } } - sched_clock_register(tegra_read_sched_clock, 32, 1000000); + sched_clock_register(tegra_read_sched_clock, 32, TIMER_1MHz); ret = clocksource_mmio_init(timer_reg_base + TIMERUS_CNTR_1US, - "timer_us", 1000000, - 300, 32, clocksource_mmio_readl_up); + "timer_us", TIMER_1MHz, 300, 32, + clocksource_mmio_readl_up); if (ret) pr_err("failed to register clocksource: %d\n", ret); |