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authorOfir Drang <ofir.drang@arm.com>2019-06-17 10:46:28 +0200
committerHerbert Xu <herbert@gondor.apana.org.au>2019-06-27 08:28:00 +0200
commitd84f6269ce24eb4c468e246b24fc0fdce34ab6f6 (patch)
treefc86b9da061c4bc7c0b7b2e1607e9e71a97ab49b /drivers/crypto/ccree/cc_driver.h
parentcrypto: ccree - Relocate driver irq registration after clk init (diff)
downloadlinux-d84f6269ce24eb4c468e246b24fc0fdce34ab6f6.tar.xz
linux-d84f6269ce24eb4c468e246b24fc0fdce34ab6f6.zip
crypto: ccree - check that cryptocell reset completed
In case of driver probe and pm resume we need to check that the cryptocell hardware reset cycle is completed. during the reset cycle that Cryptocell provide read only access to the APB interface which allows to verify through the CC registers that the reset is completed. Until reset completion we assume that any write/crypto operation is blocked. Signed-off-by: Ofir Drang <ofir.drang@arm.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
Diffstat (limited to 'drivers/crypto/ccree/cc_driver.h')
-rw-r--r--drivers/crypto/ccree/cc_driver.h3
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/crypto/ccree/cc_driver.h b/drivers/crypto/ccree/cc_driver.h
index b76181335c08..579eecae4825 100644
--- a/drivers/crypto/ccree/cc_driver.h
+++ b/drivers/crypto/ccree/cc_driver.h
@@ -67,6 +67,8 @@ enum cc_std_body {
#define CC_SECURITY_DISABLED_MASK BIT(CC_SECURITY_DISABLED_VALUE_BIT_SHIFT)
+#define CC_NVM_IS_IDLE_MASK BIT(CC_NVM_IS_IDLE_VALUE_BIT_SHIFT)
+
#define AXIM_MON_COMP_VALUE GENMASK(CC_AXIM_MON_COMP_VALUE_BIT_SIZE + \
CC_AXIM_MON_COMP_VALUE_BIT_SHIFT, \
CC_AXIM_MON_COMP_VALUE_BIT_SHIFT)
@@ -216,6 +218,7 @@ static inline void dump_byte_array(const char *name, const u8 *the_array,
__dump_byte_array(name, the_array, size);
}
+bool cc_wait_for_reset_completion(struct cc_drvdata *drvdata);
int init_cc_regs(struct cc_drvdata *drvdata, bool is_probe);
void fini_cc_regs(struct cc_drvdata *drvdata);
int cc_clk_on(struct cc_drvdata *drvdata);