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authorShukun Tan <tanshukun1@huawei.com>2020-05-15 11:13:59 +0200
committerHerbert Xu <herbert@gondor.apana.org.au>2020-05-22 16:08:22 +0200
commitc31dc9fe165d1b53c0494e0260a798d491de7bb4 (patch)
treea3526e213ef97ca4eefbb9975503b697420e2e14 /drivers/crypto/hisilicon/hpre
parentcrypto: hisilicon/zip - add debugfs for Hisilicon ZIP (diff)
downloadlinux-c31dc9fe165d1b53c0494e0260a798d491de7bb4.tar.xz
linux-c31dc9fe165d1b53c0494e0260a798d491de7bb4.zip
crypto: hisilicon/qm - add DebugFS for xQC and xQE dump
Add dump information of SQC/CQC/EQC/AEQC/SQE/CQE/EQE/AEQE. Signed-off-by: Shukun Tan <tanshukun1@huawei.com> Reviewed-by: Zhou Wang <wangzhou1@hisilicon.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
Diffstat (limited to 'drivers/crypto/hisilicon/hpre')
-rw-r--r--drivers/crypto/hisilicon/hpre/hpre_main.c4
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/crypto/hisilicon/hpre/hpre_main.c b/drivers/crypto/hisilicon/hpre/hpre_main.c
index fb3988f347f6..38405b5cb884 100644
--- a/drivers/crypto/hisilicon/hpre/hpre_main.c
+++ b/drivers/crypto/hisilicon/hpre/hpre_main.c
@@ -84,6 +84,8 @@
#define HPRE_OOO_ECC_2BIT_ERR BIT(5)
#define HPRE_VIA_MSI_DSM 1
+#define HPRE_SQE_MASK_OFFSET 8
+#define HPRE_SQE_MASK_LEN 24
static struct hisi_qm_list hpre_devices;
static const char hpre_name[] = "hisi_hpre";
@@ -683,6 +685,8 @@ static int hpre_debugfs_init(struct hpre *hpre)
dir = debugfs_create_dir(dev_name(dev), hpre_debugfs_root);
qm->debug.debug_root = dir;
+ qm->debug.sqe_mask_offset = HPRE_SQE_MASK_OFFSET;
+ qm->debug.sqe_mask_len = HPRE_SQE_MASK_LEN;
ret = hisi_qm_debug_init(qm);
if (ret)