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| author | Dan Williams <dan.j.williams@intel.com> | 2022-05-23 02:04:27 +0200 |
|---|---|---|
| committer | Dan Williams <dan.j.williams@intel.com> | 2022-07-10 01:42:44 +0200 |
| commit | 419af595b11891d632a31440b9ca5a3cdf93996d (patch) | |
| tree | a2c62cf9ce94a628e1e45d434b5851e19f409263 /drivers/cxl/cxl.h | |
| parent | cxl/core: Drop is_cxl_decoder() (diff) | |
| download | linux-419af595b11891d632a31440b9ca5a3cdf93996d.tar.xz linux-419af595b11891d632a31440b9ca5a3cdf93996d.zip | |
cxl: Introduce cxl_to_{ways,granularity}
Interleave granularity and ways have CXL specification defined encodings.
Promote the conversion helpers to a common header, and use them to
replace other open-coded instances.
Force caller to consider the error case of the conversion similarly to
other conversion helpers like kstrto*().
Co-developed-by: Ben Widawsky <bwidawsk@kernel.org>
Signed-off-by: Ben Widawsky <bwidawsk@kernel.org>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Link: https://lore.kernel.org/r/165603875016.551046.17236943065932132355.stgit@dwillia2-xfh
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Diffstat (limited to '')
| -rw-r--r-- | drivers/cxl/cxl.h | 26 |
1 files changed, 26 insertions, 0 deletions
diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h index 6e08fe8cc0fe..fd02f9e2a829 100644 --- a/drivers/cxl/cxl.h +++ b/drivers/cxl/cxl.h @@ -64,6 +64,32 @@ static inline int cxl_hdm_decoder_count(u32 cap_hdr) return val ? val * 2 : 1; } +/* Encode defined in CXL 2.0 8.2.5.12.7 HDM Decoder Control Register */ +static inline int cxl_to_granularity(u16 ig, unsigned int *val) +{ + if (ig > 6) + return -EINVAL; + *val = 256 << ig; + return 0; +} + +/* Encode defined in CXL ECN "3, 6, 12 and 16-way memory Interleaving" */ +static inline int cxl_to_ways(u8 eniw, unsigned int *val) +{ + switch (eniw) { + case 0 ... 4: + *val = 1 << eniw; + break; + case 8 ... 10: + *val = 3 << (eniw - 8); + break; + default: + return -EINVAL; + } + + return 0; +} + /* CXL 2.0 8.2.8.1 Device Capabilities Array Register */ #define CXLDEV_CAP_ARRAY_OFFSET 0x0 #define CXLDEV_CAP_ARRAY_CAP_ID 0 |