diff options
| author | Dave Jiang <dave.jiang@intel.com> | 2023-12-21 23:03:26 +0100 |
|---|---|---|
| committer | Dan Williams <dan.j.williams@intel.com> | 2023-12-22 23:33:28 +0100 |
| commit | 80aa780dda20618be76162bf991d49cf962fda38 (patch) | |
| tree | a37679f09afb8fa8af2ff7d49c35d0f0e137457f /drivers/cxl/port.c | |
| parent | cxl: Add callback to parse the DSLBIS subtable from CDAT (diff) | |
| download | linux-80aa780dda20618be76162bf991d49cf962fda38.tar.xz linux-80aa780dda20618be76162bf991d49cf962fda38.zip | |
cxl: Add callback to parse the SSLBIS subtable from CDAT
Provide a callback to parse the Switched Scoped Latency and Bandwidth
Information Structure (SSLBIS) in the CDAT structures. The SSLBIS
contains the bandwidth and latency information that's tied to the
CXL switch that the data table has been read from. The extracted
values are stored to the cxl_dport correlated by the port_id
depending on the SSLBIS entry.
Coherent Device Attribute Table 1.03 2.1 Switched Scoped Latency
and Bandwidth Information Structure (DSLBIS)
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: Dave Jiang <dave.jiang@intel.com>
Link: https://lore.kernel.org/r/170319620635.2212653.5194389158785365150.stgit@djiang5-mobl3
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Diffstat (limited to 'drivers/cxl/port.c')
| -rw-r--r-- | drivers/cxl/port.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/cxl/port.c b/drivers/cxl/port.c index a889c4e6cb27..da3c3a08bd62 100644 --- a/drivers/cxl/port.c +++ b/drivers/cxl/port.c @@ -69,6 +69,8 @@ static int cxl_switch_port_probe(struct cxl_port *port) if (rc < 0) return rc; + cxl_switch_parse_cdat(port); + cxlhdm = devm_cxl_setup_hdm(port, NULL); if (!IS_ERR(cxlhdm)) return devm_cxl_enumerate_decoders(cxlhdm, NULL); |