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| author | Sascha Hauer <s.hauer@pengutronix.de> | 2023-10-18 08:16:56 +0200 |
|---|---|---|
| committer | Chanwoo Choi <cw00.choi@samsung.com> | 2023-10-19 13:39:08 +0200 |
| commit | 74002e668d0948d12eb2283891cfbd71be9d53c6 (patch) | |
| tree | 1527f6b37c18ec00c4a2112f895a49bcb72d6e24 /drivers/devfreq/event | |
| parent | PM / devfreq: rockchip-dfi: introduce channel mask (diff) | |
| download | linux-74002e668d0948d12eb2283891cfbd71be9d53c6.tar.xz linux-74002e668d0948d12eb2283891cfbd71be9d53c6.zip | |
PM / devfreq: rk3399_dmc,dfi: generalize DDRTYPE defines
The DDRTYPE defines are named to be RK3399 specific, but they can be
used for other Rockchip SoCs as well, so replace the RK3399_PMUGRF_
prefix with ROCKCHIP_. They are defined in a SoC specific header
file, so when generalizing the prefix also move the new defines to
a SoC agnostic header file. While at it use GENMASK to define the
DDRTYPE bitfield and give it a name including the full register name.
Link: https://lore.kernel.org/all/20231018061714.3553817-9-s.hauer@pengutronix.de/
Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
Acked-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Diffstat (limited to 'drivers/devfreq/event')
| -rw-r--r-- | drivers/devfreq/event/rockchip-dfi.c | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/drivers/devfreq/event/rockchip-dfi.c b/drivers/devfreq/event/rockchip-dfi.c index 28c18bbf6baa..82d18c60538a 100644 --- a/drivers/devfreq/event/rockchip-dfi.c +++ b/drivers/devfreq/event/rockchip-dfi.c @@ -18,8 +18,10 @@ #include <linux/list.h> #include <linux/of.h> #include <linux/of_device.h> +#include <linux/bitfield.h> #include <linux/bits.h> +#include <soc/rockchip/rockchip_grf.h> #include <soc/rockchip/rk3399_grf.h> #define DMC_MAX_CHANNELS 2 @@ -75,9 +77,9 @@ static void rockchip_dfi_start_hardware_counter(struct devfreq_event_dev *edev) writel_relaxed(CLR_DDRMON_CTRL, dfi_regs + DDRMON_CTRL); /* set ddr type to dfi */ - if (dfi->ddr_type == RK3399_PMUGRF_DDRTYPE_LPDDR3) + if (dfi->ddr_type == ROCKCHIP_DDRTYPE_LPDDR3) writel_relaxed(LPDDR3_EN, dfi_regs + DDRMON_CTRL); - else if (dfi->ddr_type == RK3399_PMUGRF_DDRTYPE_LPDDR4) + else if (dfi->ddr_type == ROCKCHIP_DDRTYPE_LPDDR4) writel_relaxed(LPDDR4_EN, dfi_regs + DDRMON_CTRL); /* enable count, use software mode */ @@ -192,8 +194,7 @@ static int rk3399_dfi_init(struct rockchip_dfi *dfi) /* get ddr type */ regmap_read(regmap_pmu, RK3399_PMUGRF_OS_REG2, &val); - dfi->ddr_type = (val >> RK3399_PMUGRF_DDRTYPE_SHIFT) & - RK3399_PMUGRF_DDRTYPE_MASK; + dfi->ddr_type = FIELD_GET(RK3399_PMUGRF_OS_REG2_DDRTYPE, val); dfi->channel_mask = GENMASK(1, 0); dfi->max_channels = 2; |