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| author | Viresh Kumar <viresh.kumar@st.com> | 2011-03-03 11:17:22 +0100 |
|---|---|---|
| committer | Vinod Koul <vinod.koul@intel.com> | 2011-03-06 20:42:28 +0100 |
| commit | 93317e8e35b77633d589fe0e132291195757d785 (patch) | |
| tree | c3419c1a02e3952506ca0af281f9f9c5bc52888d /drivers/dma/dw_dmac_regs.h | |
| parent | dw_dmac: Pass Channel Allocation Order from platform_data (diff) | |
| download | linux-93317e8e35b77633d589fe0e132291195757d785.tar.xz linux-93317e8e35b77633d589fe0e132291195757d785.zip | |
dw_dmac: Pass Channel Priority from platform_data
In Synopsys designware, channel priority is programmable. This patch adds
support for passing channel priority through platform data. By default Ascending
channel priority will be followed, i.e. channel 0 will get highest priority and
channel 7 will get lowest.
Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Diffstat (limited to 'drivers/dma/dw_dmac_regs.h')
| -rw-r--r-- | drivers/dma/dw_dmac_regs.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/dma/dw_dmac_regs.h b/drivers/dma/dw_dmac_regs.h index d9a939f67f46..6a8e6d35f359 100644 --- a/drivers/dma/dw_dmac_regs.h +++ b/drivers/dma/dw_dmac_regs.h @@ -101,6 +101,8 @@ struct dw_dma_regs { #define DWC_CTLH_BLOCK_TS_MASK 0x00000fff /* Bitfields in CFG_LO. Platform-configurable bits are in <linux/dw_dmac.h> */ +#define DWC_CFGL_CH_PRIOR_MASK (0x7 << 5) /* priority mask */ +#define DWC_CFGL_CH_PRIOR(x) ((x) << 5) /* priority */ #define DWC_CFGL_CH_SUSP (1 << 8) /* pause xfer */ #define DWC_CFGL_FIFO_EMPTY (1 << 9) /* pause xfer */ #define DWC_CFGL_HS_DST (1 << 10) /* handshake w/dst */ @@ -134,6 +136,7 @@ struct dw_dma_chan { struct dma_chan chan; void __iomem *ch_regs; u8 mask; + u8 priority; spinlock_t lock; |