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authorForrest Shi <b29237@freescale.com>2010-12-09 09:14:04 +0100
committerDan Williams <dan.j.williams@intel.com>2010-12-13 23:05:27 +0100
commitf3c677b997757326e1f29d33060719a6a5091950 (patch)
tree3135e7ee4a04d5abd929cc863168c0c6a574e824 /drivers/dma/fsldma.c
parentdmaengine i.MX SDMA: initialize on module_init (diff)
downloadlinux-f3c677b997757326e1f29d33060719a6a5091950.tar.xz
linux-f3c677b997757326e1f29d33060719a6a5091950.zip
fsldma: fix issue of slow dma
Fixed fsl dma slow issue by initializing dma mode register with bandwidth control. It boosts dma performance and should works with 85xx board. Signed-off-by: Forrest Shi <b29237@freescale.com> Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Diffstat (limited to 'drivers/dma/fsldma.c')
-rw-r--r--drivers/dma/fsldma.c6
1 files changed, 4 insertions, 2 deletions
diff --git a/drivers/dma/fsldma.c b/drivers/dma/fsldma.c
index 286c3ac6bdcc..e5e172d21692 100644
--- a/drivers/dma/fsldma.c
+++ b/drivers/dma/fsldma.c
@@ -50,9 +50,11 @@ static void dma_init(struct fsldma_chan *chan)
* EIE - Error interrupt enable
* EOSIE - End of segments interrupt enable (basic mode)
* EOLNIE - End of links interrupt enable
+ * BWC - Bandwidth sharing among channels
*/
- DMA_OUT(chan, &chan->regs->mr, FSL_DMA_MR_EIE
- | FSL_DMA_MR_EOLNIE | FSL_DMA_MR_EOSIE, 32);
+ DMA_OUT(chan, &chan->regs->mr, FSL_DMA_MR_BWC
+ | FSL_DMA_MR_EIE | FSL_DMA_MR_EOLNIE
+ | FSL_DMA_MR_EOSIE, 32);
break;
case FSL_DMA_IP_83XX:
/* Set the channel to below modes: