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| author | Andy Shevchenko <andriy.shevchenko@linux.intel.com> | 2016-03-18 13:26:35 +0100 |
|---|---|---|
| committer | Vinod Koul <vinod.koul@intel.com> | 2016-04-04 18:42:00 +0200 |
| commit | c36a0176ba678fd1a4bf985fd62f43dd4f4d4a03 (patch) | |
| tree | 0436bc008ddbc9272859b7e3416e9289ed50d16a /drivers/dma/hsu/hsu.c | |
| parent | dmaengine: hsu: allow more than 3 descriptors (diff) | |
| download | linux-c36a0176ba678fd1a4bf985fd62f43dd4f4d4a03.tar.xz linux-c36a0176ba678fd1a4bf985fd62f43dd4f4d4a03.zip | |
dmaengine: hsu: don't check direction of timeouted channel
The timeout capability is only available on the so called DMA write channels,
i.e. associated with UART Rx FIFO. It means we don't need to check the
direction of the channel to handle timeouts.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Diffstat (limited to 'drivers/dma/hsu/hsu.c')
| -rw-r--r-- | drivers/dma/hsu/hsu.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/dma/hsu/hsu.c b/drivers/dma/hsu/hsu.c index 6fce5ed2fc40..1817b7bc9576 100644 --- a/drivers/dma/hsu/hsu.c +++ b/drivers/dma/hsu/hsu.c @@ -160,7 +160,7 @@ irqreturn_t hsu_dma_irq(struct hsu_dma_chip *chip, unsigned short nr) return IRQ_NONE; /* Timeout IRQ, need wait some time, see Errata 2 */ - if (hsuc->direction == DMA_DEV_TO_MEM && (sr & HSU_CH_SR_DESCTO_ANY)) + if (sr & HSU_CH_SR_DESCTO_ANY) udelay(2); sr &= ~HSU_CH_SR_DESCTO_ANY; |