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authorMisael Lopez Cruz <misael.lopez@ti.com>2015-09-14 14:31:05 +0200
committerVinod Koul <vinod.koul@intel.com>2015-10-05 17:31:34 +0200
commit47fac2415db653a79e005d4fa25948d3667b8e02 (patch)
treef33dba10a503995de6f56558d00914fbf4fece74 /drivers/dma/omap-dma.c
parentdmaengine: xilinx: Fix module autoload for OF platform driver (diff)
downloadlinux-47fac2415db653a79e005d4fa25948d3667b8e02.tar.xz
linux-47fac2415db653a79e005d4fa25948d3667b8e02.zip
dmaengine: omap-dma: Enable packed accesses for cyclic transfers
The L3 throughput can be higher than expected when packed access is not enabled. The ratio depends on the number of bytes in a transaction and the EMIF interface width. The throughput was measured for the following settings/cases: * Case 1: Burst size of 64 bytes, packed access disabled * Case 2: Burst size of 64 bytes, packed access enabled * Case 3: Burst disabled, packed access disabled Throughput measurements were done during McASP-based audio playback on the Jacinto6 EVM using the omapconf tool [1]: $ omapconf trace bw -m sdma_rd --------------------------------------------------------- Throughput (MB/s) Audio parameters Case 1 Case 2 Case 3 --------------------------------------------------------- 44.1kHz, 16-bits, stereo 1.41 0.18 1.41 44.1kHz, 32-bits, stereo 1.41 0.35 1.41 44.1kHz, 16-bits, 4-chan 2.82 0.35 2.82 44.1kHz, 16-bits, 6-chan 4.23 0.53 4.23 44.1kHz, 16-bits, 8-chan 5.64 0.71 5.64 --------------------------------------------------------- From above measurements, case 2 is the only one that delivers the expected throughput for the given audio parameters. For that reason, the packed accesses are now enabled. It's worth to mention that packed accesses cannot be enabled for all addressing modes. In cyclic transfers, it can be enabled in the source for MEM_TO_DEV and in dest for DEV_TO_MEM, as they use post-increment mode which supports packed accesses. Peter Ujfalusi: From the TRM regarding to this: "NOTE: Except in the constant addressing mode, the source or destination must be specified as packed for burst transactions to occur." So w/o the packed setting the burst on the MEM side was not enabled, this explains the numbers. [1] https://github.com/omapconf/omapconf Signed-off-by: Misael Lopez Cruz <misael.lopez@ti.com> Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Diffstat (limited to 'drivers/dma/omap-dma.c')
-rw-r--r--drivers/dma/omap-dma.c6
1 files changed, 5 insertions, 1 deletions
diff --git a/drivers/dma/omap-dma.c b/drivers/dma/omap-dma.c
index 249445c8a4c6..1dfc71c90123 100644
--- a/drivers/dma/omap-dma.c
+++ b/drivers/dma/omap-dma.c
@@ -935,8 +935,12 @@ static struct dma_async_tx_descriptor *omap_dma_prep_dma_cyclic(
else
d->ccr |= CCR_SYNC_ELEMENT;
- if (dir == DMA_DEV_TO_MEM)
+ if (dir == DMA_DEV_TO_MEM) {
d->ccr |= CCR_TRIGGER_SRC;
+ d->csdp |= CSDP_DST_PACKED;
+ } else {
+ d->csdp |= CSDP_SRC_PACKED;
+ }
d->cicr |= CICR_MISALIGNED_ERR_IE | CICR_TRANS_ERR_IE;