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| author | Stefan Brüns <stefan.bruens@rwth-aachen.de> | 2017-09-28 03:49:25 +0200 |
|---|---|---|
| committer | Vinod Koul <vinod.koul@intel.com> | 2017-10-16 09:01:36 +0200 |
| commit | 12e0177055ee4b5ab656414b32054e64568160d8 (patch) | |
| tree | add909df6c4dcbced8de8ba63ab86deebc987749 /drivers/dma/sun6i-dma.c | |
| parent | arm64: allwinner: a64: Add devicetree binding for DMA controller (diff) | |
| download | linux-12e0177055ee4b5ab656414b32054e64568160d8.tar.xz linux-12e0177055ee4b5ab656414b32054e64568160d8.zip | |
dmaengine: sun6i: Add support for Allwinner A64 and compatibles
The A64 SoC has the same dma engine as the H3 (sun8i), with a
reduced amount of physical channels. To allow future reuse of the
compatible, leave the channel count etc. in the config data blank
and retrieve it from the devicetree.
Signed-off-by: Stefan Brüns <stefan.bruens@rwth-aachen.de>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Diffstat (limited to 'drivers/dma/sun6i-dma.c')
| -rw-r--r-- | drivers/dma/sun6i-dma.c | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/drivers/dma/sun6i-dma.c b/drivers/dma/sun6i-dma.c index f27b126dd6cd..0cabb48b0fb5 100644 --- a/drivers/dma/sun6i-dma.c +++ b/drivers/dma/sun6i-dma.c @@ -1122,6 +1122,25 @@ static struct sun6i_dma_config sun8i_h3_dma_cfg = { }; /* + * The A64 binding uses the number of dma channels from the + * device tree node. + */ +static struct sun6i_dma_config sun50i_a64_dma_cfg = { + .clock_autogate_enable = sun6i_enable_clock_autogate_h3, + .set_burst_length = sun6i_set_burst_length_h3, + .src_burst_lengths = BIT(1) | BIT(4) | BIT(8) | BIT(16), + .dst_burst_lengths = BIT(1) | BIT(4) | BIT(8) | BIT(16), + .src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | + BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | + BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | + BIT(DMA_SLAVE_BUSWIDTH_8_BYTES), + .dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | + BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | + BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | + BIT(DMA_SLAVE_BUSWIDTH_8_BYTES), +}; + +/* * The V3s have only 8 physical channels, a maximum DRQ port id of 23, * and a total of 24 usable source and destination endpoints. */ @@ -1148,6 +1167,7 @@ static const struct of_device_id sun6i_dma_match[] = { { .compatible = "allwinner,sun8i-a83t-dma", .data = &sun8i_a83t_dma_cfg }, { .compatible = "allwinner,sun8i-h3-dma", .data = &sun8i_h3_dma_cfg }, { .compatible = "allwinner,sun8i-v3s-dma", .data = &sun8i_v3s_dma_cfg }, + { .compatible = "allwinner,sun50i-a64-dma", .data = &sun50i_a64_dma_cfg }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, sun6i_dma_match); |