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| author | Kedareswara rao Appana <appana.durga.rao@xilinx.com> | 2016-07-09 10:39:48 +0200 |
|---|---|---|
| committer | Vinod Koul <vinod.koul@intel.com> | 2016-07-12 06:31:36 +0200 |
| commit | e598e6eb46dd448d9b77a564e4d9664da52e3e1f (patch) | |
| tree | 18c321dfa37a0be4732ef555f554b802bf68c855 /drivers/dma/xilinx/xilinx_dma.c | |
| parent | dmaengine: Add Xilinx zynqmp dma engine driver support (diff) | |
| download | linux-e598e6eb46dd448d9b77a564e4d9664da52e3e1f.tar.xz linux-e598e6eb46dd448d9b77a564e4d9664da52e3e1f.zip | |
dmaengine: xilinx: Fix race condition in axi dma cyclic dma mode
In cyclic DMA mode need to link the tail bd segment
with the head bd segment to process bd's in cyclic.
Current driver is doing this only for tx channel
needs to update the same for rx channel case also.
This patch fixes the same.
Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Diffstat (limited to 'drivers/dma/xilinx/xilinx_dma.c')
| -rw-r--r-- | drivers/dma/xilinx/xilinx_dma.c | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/drivers/dma/xilinx/xilinx_dma.c b/drivers/dma/xilinx/xilinx_dma.c index cf47347a1bc6..4e223d094433 100644 --- a/drivers/dma/xilinx/xilinx_dma.c +++ b/drivers/dma/xilinx/xilinx_dma.c @@ -1895,14 +1895,15 @@ static struct dma_async_tx_descriptor *xilinx_dma_prep_dma_cyclic( reg |= XILINX_DMA_CR_CYCLIC_BD_EN_MASK; dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, reg); + segment = list_last_entry(&desc->segments, + struct xilinx_axidma_tx_segment, + node); + segment->hw.next_desc = (u32) head_segment->phys; + /* For the last DMA_MEM_TO_DEV transfer, set EOP */ if (direction == DMA_MEM_TO_DEV) { head_segment->hw.control |= XILINX_DMA_BD_SOP; - segment = list_last_entry(&desc->segments, - struct xilinx_axidma_tx_segment, - node); segment->hw.control |= XILINX_DMA_BD_EOP; - segment->hw.next_desc = (u32) head_segment->phys; } return &desc->async_tx; |