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authorYash Shah <yash.shah@sifive.com>2019-05-06 13:27:06 +0200
committerTony Luck <tony.luck@intel.com>2019-06-20 20:44:36 +0200
commit91abaeaaff35d97e88d2249f69f19db749a19a68 (patch)
tree9173bac76607319c7fdb1587609750b9d7fb04a0 /drivers/edac/Kconfig
parentEDAC/sb_edac: Remove redundant update of tad_base (diff)
downloadlinux-91abaeaaff35d97e88d2249f69f19db749a19a68.tar.xz
linux-91abaeaaff35d97e88d2249f69f19db749a19a68.zip
EDAC/sifive: Add EDAC platform driver for SiFive SoCs
Add an EDAC driver for SiFive SoCs. The initial version supports ECC event monitoring and reporting through the EDAC framework for the SiFive L2 cache controller. It registers for notifier events from the L2 cache controller driver (arch/riscv/mm/sifive_l2_cache.c) for L2 ECC events. [ bp: Massage commit message. ] Signed-off-by: Yash Shah <yash.shah@sifive.com> Signed-off-by: Borislav Petkov <bp@suse.de> Reviewed-by: James Morse <james.morse@arm.com> Cc: Albert Ou <aou@eecs.berkeley.edu> Cc: "David S. Miller" <davem@davemloft.net> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Cc: Jonathan Cameron <Jonathan.Cameron@huawei.com> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: linux-edac <linux-edac@vger.kernel.org> Cc: linux-riscv@lists.infradead.org Cc: Mauro Carvalho Chehab <mchehab@kernel.org> Cc: Nicolas Ferre <nicolas.ferre@microchip.com> Cc: Palmer Dabbelt <palmer@sifive.com> Cc: "Paul E. McKenney" <paulmck@linux.ibm.com> Cc: Paul Walmsley <paul.walmsley@sifive.com> Cc: sachin.ghadi@sifive.com Link: https://lkml.kernel.org/r/1557142026-15949-2-git-send-email-yash.shah@sifive.com
Diffstat (limited to 'drivers/edac/Kconfig')
-rw-r--r--drivers/edac/Kconfig6
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig
index 5e2e0348d460..200c04ce5b0e 100644
--- a/drivers/edac/Kconfig
+++ b/drivers/edac/Kconfig
@@ -460,6 +460,12 @@ config EDAC_ALTERA_SDMMC
Support for error detection and correction on the
Altera SDMMC FIFO Memory for Altera SoCs.
+config EDAC_SIFIVE
+ bool "Sifive platform EDAC driver"
+ depends on EDAC=y && RISCV
+ help
+ Support for error detection and correction on the SiFive SoCs.
+
config EDAC_SYNOPSYS
tristate "Synopsys DDR Memory Controller"
depends on ARCH_ZYNQ || ARCH_ZYNQMP