diff options
| author | Thor Thayer <tthayer@opensource.altera.com> | 2016-03-21 17:01:44 +0100 |
|---|---|---|
| committer | Borislav Petkov <bp@suse.de> | 2016-03-29 10:34:06 +0200 |
| commit | 588cb03ea208b303e6dee7e916f329043fd0fc26 (patch) | |
| tree | acc1e591b446c8bee8016c33f6b7fbf8bf277b8c /drivers/edac/altera_edac.h | |
| parent | Documentation, dt, socfpga: Add Altera Arria10 L2 cache binding (diff) | |
| download | linux-588cb03ea208b303e6dee7e916f329043fd0fc26.tar.xz linux-588cb03ea208b303e6dee7e916f329043fd0fc26.zip | |
EDAC, altera: Add Arria10 L2 Cache ECC handling
Add a private data structure for Arria10 L2 cache ECC and the probe
function for it.
The Arria10 ECC device IRQs are in a shared register so the ECC Manager
parent/child relationship requires a different probe function.
Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>
Cc: devicetree@vger.kernel.org
Cc: dinguyen@opensource.altera.com
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux@arm.linux.org.uk
Cc: linux-edac <linux-edac@vger.kernel.org>
Link: http://lkml.kernel.org/r/1458576106-24505-8-git-send-email-tthayer@opensource.altera.com
Signed-off-by: Borislav Petkov <bp@suse.de>
Diffstat (limited to 'drivers/edac/altera_edac.h')
| -rw-r--r-- | drivers/edac/altera_edac.h | 42 |
1 files changed, 42 insertions, 0 deletions
diff --git a/drivers/edac/altera_edac.h b/drivers/edac/altera_edac.h index d7ef94c13b98..b0a17d03c715 100644 --- a/drivers/edac/altera_edac.h +++ b/drivers/edac/altera_edac.h @@ -219,12 +219,39 @@ struct altr_sdram_mc_data { #define ALTR_L2_ECC_INJS BIT(1) #define ALTR_L2_ECC_INJD BIT(2) +/* Arria10 General ECC Block Module Defines */ +#define A10_SYSMGR_ECC_INTSTAT_SERR_OFST 0x9C +#define A10_SYSMGR_ECC_INTSTAT_DERR_OFST 0xA0 +#define A10_SYSMGR_ECC_INTSTAT_L2 BIT(0) + +#define A10_SYSGMR_MPU_CLEAR_L2_ECC_OFST 0xA8 +#define A10_SYSGMR_MPU_CLEAR_L2_ECC_SB BIT(15) +#define A10_SYSGMR_MPU_CLEAR_L2_ECC_MB BIT(31) + +/* Arria 10 L2 ECC Management Group Defines */ +#define ALTR_A10_L2_ECC_CTL_OFST 0x0 +#define ALTR_A10_L2_ECC_EN_CTL BIT(0) + +#define ALTR_A10_L2_ECC_STATUS 0xFFD060A4 +#define ALTR_A10_L2_ECC_STAT_OFST 0xA4 +#define ALTR_A10_L2_ECC_SERR_PEND BIT(0) +#define ALTR_A10_L2_ECC_MERR_PEND BIT(0) + +#define ALTR_A10_L2_ECC_CLR_OFST 0x4 +#define ALTR_A10_L2_ECC_SERR_CLR BIT(15) +#define ALTR_A10_L2_ECC_MERR_CLR BIT(31) + +#define ALTR_A10_L2_ECC_INJ_OFST ALTR_A10_L2_ECC_CTL_OFST +#define ALTR_A10_L2_ECC_CE_INJ_MASK 0x00000101 +#define ALTR_A10_L2_ECC_UE_INJ_MASK 0x00010101 + struct altr_edac_device_dev; struct edac_device_prv_data { int (*setup)(struct altr_edac_device_dev *device); int ce_clear_mask; int ue_clear_mask; + int irq_status_mask; char dbgfs_name[20]; void * (*alloc_mem)(size_t size, void **other); void (*free_mem)(void *p, size_t size, void *other); @@ -232,16 +259,31 @@ struct edac_device_prv_data { int ce_set_mask; int ue_set_mask; int set_err_ofst; + irqreturn_t (*ecc_irq_handler)(struct altr_edac_device_dev *dci, + bool sb); int trig_alloc_sz; }; struct altr_edac_device_dev { + struct list_head next; void __iomem *base; int sb_irq; int db_irq; const struct edac_device_prv_data *data; struct dentry *debugfs_dir; char *edac_dev_name; + struct altr_arria10_edac *edac; + struct edac_device_ctl_info *edac_dev; + struct device ddev; + int edac_idx; +}; + +struct altr_arria10_edac { + struct device *dev; + struct regmap *ecc_mgr_map; + int sb_irq; + int db_irq; + struct list_head a10_ecc_devices; }; #endif /* #ifndef _ALTERA_EDAC_H */ |