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authorBorislav Petkov <borislav.petkov@amd.com>2009-07-28 10:56:15 +0200
committerBorislav Petkov <borislav.petkov@amd.com>2009-09-14 19:01:20 +0200
commitd93cc222adf3532ddb442648f8db00c15d1dc4c1 (patch)
tree57e0ac9280bff2b824a066621a3009ea7f9835ea /drivers/edac/amd64_edac.c
parentEDAC, AMD: carve out MCi_STATUS decoding (diff)
downloadlinux-d93cc222adf3532ddb442648f8db00c15d1dc4c1.tar.xz
linux-d93cc222adf3532ddb442648f8db00c15d1dc4c1.zip
EDAC, AMD: carve out decoding of MCi_STATUS ErrorCode
This is the MCE error code from the MCi_STATUS banks, bits [15:0] which describe what type of error was encountered: GART TLB, Memory or Bus error. The semantics of those bits are identical across all MCE banks so decode those separately, irrespectively of MCE type. Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
Diffstat (limited to 'drivers/edac/amd64_edac.c')
-rw-r--r--drivers/edac/amd64_edac.c4
1 files changed, 0 insertions, 4 deletions
diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c
index c81ca2cf8dc7..173dc4a84166 100644
--- a/drivers/edac/amd64_edac.c
+++ b/drivers/edac/amd64_edac.c
@@ -2289,10 +2289,6 @@ static inline void __amd64_decode_bus_error(struct mem_ctl_info *mci,
u32 xec = EXT_ERROR_CODE(info->nbsl);
int ecc_type = info->nbsh & (0x3 << 13);
- pr_emerg(" Transaction type: %s(%s), %s, Cache Level: %s, %s\n",
- RRRR_MSG(ec), II_MSG(ec), TO_MSG(ec), LL_MSG(ec), PP_MSG(ec));
-
-
/* Bail early out if this was an 'observed' error */
if (PP(ec) == K8_NBSL_PP_OBS)
return;