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| author | Borislav Petkov <borislav.petkov@amd.com> | 2011-01-18 19:16:08 +0100 |
|---|---|---|
| committer | Borislav Petkov <borislav.petkov@amd.com> | 2011-03-17 14:46:24 +0100 |
| commit | 41d8bfaba70311c2fa0666554ef160ea8ffc9daf (patch) | |
| tree | 87b236d16240872304638ed0011bb2a9c244c0ee /drivers/edac/amd64_edac.h | |
| parent | amd64_edac: Sanitize ->read_dram_ctl_register (diff) | |
| download | linux-41d8bfaba70311c2fa0666554ef160ea8ffc9daf.tar.xz linux-41d8bfaba70311c2fa0666554ef160ea8ffc9daf.zip | |
amd64_edac: Improve DRAM address mapping
Drop static tables which map the bits in F2x80 to a chip select size in
favor of functions doing the mapping with some bit fiddling. Also, add
F15 support.
Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
Diffstat (limited to 'drivers/edac/amd64_edac.h')
| -rw-r--r-- | drivers/edac/amd64_edac.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/edac/amd64_edac.h b/drivers/edac/amd64_edac.h index e14a8d0ad19f..8e431ab6a983 100644 --- a/drivers/edac/amd64_edac.h +++ b/drivers/edac/amd64_edac.h @@ -221,7 +221,7 @@ #define DCLR0 0x90 #define DCLR1 0x190 #define REVE_WIDTH_128 BIT(16) -#define F10_WIDTH_128 BIT(11) +#define WIDTH_128 BIT(11) #define DCHR0 0x94 #define DCHR1 0x194 @@ -445,7 +445,7 @@ struct low_ops { int (*early_channel_count) (struct amd64_pvt *pvt); void (*map_sysaddr_to_csrow) (struct mem_ctl_info *mci, u64 sys_addr, u16 syndrome); - int (*dbam_to_cs) (struct amd64_pvt *pvt, int cs_mode); + int (*dbam_to_cs) (struct amd64_pvt *pvt, u8 dct, unsigned cs_mode); int (*read_dct_pci_cfg) (struct amd64_pvt *pvt, int offset, u32 *val, const char *func); }; |