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authorYazen Ghannam <Yazen.Ghannam@amd.com>2016-11-17 23:57:34 +0100
committerBorislav Petkov <bp@suse.de>2016-11-24 21:07:03 +0100
commit196b79fcc8ed4e3c565a746b06125596bee06b62 (patch)
tree827918d113130cb7fd987f87e6a41ffd38548045 /drivers/edac/amd64_edac.h
parentMerge tip:ras/core to pick up dependent changes (diff)
downloadlinux-196b79fcc8ed4e3c565a746b06125596bee06b62.tar.xz
linux-196b79fcc8ed4e3c565a746b06125596bee06b62.zip
EDAC, amd64: Extend ecc_enabled() to Fam17h
Update the ecc_enabled() function to work on Fam17h. This entails reading a different set of registers and using the SMN (System Management Network) rather than PCI devices. Signed-off-by: Yazen Ghannam <Yazen.Ghannam@amd.com> Cc: Aravind Gopalakrishnan <aravindksg.lkml@gmail.com> Cc: linux-edac <linux-edac@vger.kernel.org> Cc: x86-ml <x86@kernel.org> Link: http://lkml.kernel.org/r/1479423463-8536-9-git-send-email-Yazen.Ghannam@amd.com [ Fixup ecc_en assignment and get_umc_base(). ] Signed-off-by: Borislav Petkov <bp@suse.de>
Diffstat (limited to 'drivers/edac/amd64_edac.h')
-rw-r--r--drivers/edac/amd64_edac.h16
1 files changed, 16 insertions, 0 deletions
diff --git a/drivers/edac/amd64_edac.h b/drivers/edac/amd64_edac.h
index c08870479054..96c1f5d6d130 100644
--- a/drivers/edac/amd64_edac.h
+++ b/drivers/edac/amd64_edac.h
@@ -248,6 +248,16 @@
/* MSRs */
#define MSR_MCGCTL_NBE BIT(4)
+/* UMC CH register offsets */
+#define UMCCH_SDP_CTRL 0x104
+#define UMCCH_UMC_CAP_HI 0xDF4
+
+/* UMC CH bitfields */
+#define UMC_ECC_ENABLED BIT(30)
+#define UMC_SDP_INIT BIT(31)
+
+#define NUM_UMCS 2
+
enum amd_families {
K8_CPUS = 0,
F10_CPUS,
@@ -354,6 +364,12 @@ struct err_info {
u32 offset;
};
+static inline u32 get_umc_base(u8 channel)
+{
+ /* ch0: 0x50000, ch1: 0x150000 */
+ return 0x50000 + (!!channel << 20);
+}
+
static inline u64 get_dram_base(struct amd64_pvt *pvt, u8 i)
{
u64 addr = ((u64)pvt->ranges[i].base.lo & 0xffff0000) << 8;