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| author | Borislav Petkov <bp@suse.de> | 2019-04-25 16:30:34 +0200 |
|---|---|---|
| committer | Borislav Petkov <bp@suse.de> | 2019-04-25 16:30:34 +0200 |
| commit | 8de9930a4618811edfaebc4981a9fafff2af9170 (patch) | |
| tree | 4a57cfdb6282e1e8f788118829a1442f293d7814 /drivers/edac/amd64_edac.h | |
| parent | arm64: dts: stratix10: Use new Stratix10 EDAC bindings (diff) | |
| download | linux-8de9930a4618811edfaebc4981a9fafff2af9170.tar.xz linux-8de9930a4618811edfaebc4981a9fafff2af9170.zip | |
Revert "EDAC/amd64: Support more than two controllers for chip select handling"
This reverts commit 0a227af521d6df5286550b62f4b591417170b4ea.
Unfortunately, this commit caused wrong detection of chip select sizes
on some F17h client machines:
--- 00-rc6+ 2019-02-14 14:28:03.126622904 +0100
+++ 01-rc4+ 2019-04-14 21:06:16.060614790 +0200
EDAC amd64: MC: 0: 0MB 1: 0MB
-EDAC amd64: MC: 2: 16383MB 3: 16383MB
+EDAC amd64: MC: 2: 0MB 3: 2097151MB
EDAC amd64: MC: 4: 0MB 5: 0MB
EDAC amd64: MC: 6: 0MB 7: 0MB
EDAC MC: UMC1 chip selects:
EDAC amd64: MC: 0: 0MB 1: 0MB
-EDAC amd64: MC: 2: 16383MB 3: 16383MB
+EDAC amd64: MC: 2: 0MB 3: 2097151MB
EDAC amd64: MC: 4: 0MB 5: 0MB
EDAC amd64: MC: 6: 0MB 7: 0M
Revert it for now until it has been solved properly.
Signed-off-by: Borislav Petkov <bp@suse.de>
Cc: Yazen Ghannam <yazen.ghannam@amd.com>
Diffstat (limited to 'drivers/edac/amd64_edac.h')
| -rw-r--r-- | drivers/edac/amd64_edac.h | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/drivers/edac/amd64_edac.h b/drivers/edac/amd64_edac.h index 4dce6a2ac75f..8f66472f7adc 100644 --- a/drivers/edac/amd64_edac.h +++ b/drivers/edac/amd64_edac.h @@ -96,7 +96,6 @@ /* Hardware limit on ChipSelect rows per MC and processors per system */ #define NUM_CHIPSELECTS 8 #define DRAM_RANGES 8 -#define NUM_CONTROLLERS 8 #define ON true #define OFF false @@ -352,8 +351,8 @@ struct amd64_pvt { u32 dbam0; /* DRAM Base Address Mapping reg for DCT0 */ u32 dbam1; /* DRAM Base Address Mapping reg for DCT1 */ - /* one for each DCT/UMC */ - struct chip_select csels[NUM_CONTROLLERS]; + /* one for each DCT */ + struct chip_select csels[2]; /* DRAM base and limit pairs F1x[78,70,68,60,58,50,48,40] */ struct dram_range ranges[DRAM_RANGES]; |