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authorBorislav Petkov <borislav.petkov@amd.com>2011-02-23 17:25:12 +0100
committerBorislav Petkov <borislav.petkov@amd.com>2011-03-17 14:46:34 +0100
commit8c6717510f8002ea31b309c84b7d7a7f7c15197b (patch)
tree6fda1db2bb648c5ae7f446e3bedabd78da098fa5 /drivers/edac
parentamd64_edac: Fix ranges signedness (diff)
downloadlinux-8c6717510f8002ea31b309c84b7d7a7f7c15197b.tar.xz
linux-8c6717510f8002ea31b309c84b7d7a7f7c15197b.zip
amd64_edac: Fix DCT argument type
Fix amd64_debug_display_dimm_sizes() arguments order per convention (pvt is always first). Also, the now second arg denotes the DCT so adjust its type. Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
Diffstat (limited to 'drivers/edac')
-rw-r--r--drivers/edac/amd64_edac.c9
1 files changed, 4 insertions, 5 deletions
diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c
index 1b8fa7a905eb..cc4f887c28f0 100644
--- a/drivers/edac/amd64_edac.c
+++ b/drivers/edac/amd64_edac.c
@@ -768,8 +768,7 @@ static enum edac_type amd64_determine_edac_cap(struct amd64_pvt *pvt)
return edac_cap;
}
-
-static void amd64_debug_display_dimm_sizes(int ctrl, struct amd64_pvt *pvt);
+static void amd64_debug_display_dimm_sizes(struct amd64_pvt *, u8);
static void amd64_dump_dramcfg_low(u32 dclr, int chan)
{
@@ -817,13 +816,13 @@ static void dump_misc_regs(struct amd64_pvt *pvt)
debugf1(" DramHoleValid: %s\n", dhar_valid(pvt) ? "yes" : "no");
- amd64_debug_display_dimm_sizes(0, pvt);
+ amd64_debug_display_dimm_sizes(pvt, 0);
/* everything below this point is Fam10h and above */
if (boot_cpu_data.x86 == 0xf)
return;
- amd64_debug_display_dimm_sizes(1, pvt);
+ amd64_debug_display_dimm_sizes(pvt, 1);
amd64_info("using %s syndromes.\n", ((pvt->ecc_sym_sz == 8) ? "x8" : "x4"));
@@ -1536,7 +1535,7 @@ static void f1x_map_sysaddr_to_csrow(struct mem_ctl_info *mci, u64 sys_addr,
* debug routine to display the memory sizes of all logical DIMMs and its
* CSROWs
*/
-static void amd64_debug_display_dimm_sizes(int ctrl, struct amd64_pvt *pvt)
+static void amd64_debug_display_dimm_sizes(struct amd64_pvt *pvt, u8 ctrl)
{
int dimm, size0, size1, factor = 0;
u32 *dcsb = ctrl ? pvt->csels[1].csbases : pvt->csels[0].csbases;