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authorValentin Longchamp <valentin.longchamp@keymile.com>2017-02-17 11:29:46 +0100
committerScott Wood <oss@buserror.net>2017-04-30 08:31:52 +0200
commite5c5c8d23fef2a976afe724f30e34da31be09769 (patch)
treedaaf87e69a71dd611f96cce73cfbdb80239a9257 /drivers/firewire
parentsoc/fsl/qe: round brg_freq to 1kHz granularity (diff)
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soc/fsl/qe: only apply QE_General4 workaround on affected SoCs
The QE_General4 workaround is only valid for the MPC832x and MPC836x SoCs. The other SoCs that embed a QUICC engine are not affected by this hardware bug and thus can use the computed divisors (this was successfully tested on the T1040). Similalry to what was done in commit 8ce795cb0c6b ("i2c: mpc: assign the correct prescaler from SVR") in order to avoid changes in the device tree nodes of the QE (with maybe a variant of the compatible property), the PVR reg is read out to find out if the workaround must be applied or not. Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com> Signed-off-by: Scott Wood <oss@buserror.net>
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