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| author | Wu Hao <hao.wu@intel.com> | 2018-06-30 02:53:17 +0200 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2018-07-15 13:55:45 +0200 |
| commit | 6e8fd6e493bfca83021cc6a8fd86d7f69bd14fc6 (patch) | |
| tree | af3fbc09c6a38add8eac0c811ee6b80c624f3b7f /drivers/fpga/dfl.h | |
| parent | fpga: dfl: add feature device infrastructure (diff) | |
| download | linux-6e8fd6e493bfca83021cc6a8fd86d7f69bd14fc6.tar.xz linux-6e8fd6e493bfca83021cc6a8fd86d7f69bd14fc6.zip | |
fpga: dfl: add dfl_fpga_port_ops support.
In some cases, other DFL driver modules may need to access some port
operations, e.g. disable / enable port for partial reconfiguration in
FME module. In order to avoid dependency between port and FME modules,
this patch introduces the dfl_fpga_port_ops support in DFL framework.
A global dfl_fpga_port_ops list is added in the DFL framework, and
it allows other DFL modules to use these port operations registered
to this list, even in virtualization case, the port platform device
is turned into VF / guest VM and hidden in host, the registered
port_ops is still usable. It resolves the dependency issues between
modules, but once get port ops API returns a valid port ops, that
means related port driver module has been module_get to prevent from
unexpected unload, and put port ops API must be invoked after use.
These APIs introduced by this patch is listed below:
* dfl_fpga_port_ops_add
add one port ops to the global list.
* dfl_fpga_port_ops_del
del one port ops from the global list.
* dfl_fpga_port_ops_get / dfl_fpga_port_ops_put
get/put the port ops before/after use.
Signed-off-by: Wu Hao <hao.wu@intel.com>
Acked-by: Alan Tull <atull@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to '')
| -rw-r--r-- | drivers/fpga/dfl.h | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/drivers/fpga/dfl.h b/drivers/fpga/dfl.h index 14d4731c13b0..654e0f694a5f 100644 --- a/drivers/fpga/dfl.h +++ b/drivers/fpga/dfl.h @@ -130,6 +130,27 @@ /* Latency tolerance reporting. '1' >= 40us, '0' < 40us.*/ #define PORT_CTRL_LATENCY BIT_ULL(2) #define PORT_CTRL_SFTRST_ACK BIT_ULL(4) /* HW ack for reset */ +/** + * struct dfl_fpga_port_ops - port ops + * + * @name: name of this port ops, to match with port platform device. + * @owner: pointer to the module which owns this port ops. + * @node: node to link port ops to global list. + * @get_id: get port id from hardware. + * @enable_set: enable/disable the port. + */ +struct dfl_fpga_port_ops { + const char *name; + struct module *owner; + struct list_head node; + int (*get_id)(struct platform_device *pdev); + int (*enable_set)(struct platform_device *pdev, bool enable); +}; + +void dfl_fpga_port_ops_add(struct dfl_fpga_port_ops *ops); +void dfl_fpga_port_ops_del(struct dfl_fpga_port_ops *ops); +struct dfl_fpga_port_ops *dfl_fpga_port_ops_get(struct platform_device *pdev); +void dfl_fpga_port_ops_put(struct dfl_fpga_port_ops *ops); /** * struct dfl_feature_driver - sub feature's driver |