diff options
| author | Andy Shevchenko <andriy.shevchenko@linux.intel.com> | 2016-07-11 12:06:26 +0200 |
|---|---|---|
| committer | Linus Walleij <linus.walleij@linaro.org> | 2016-07-22 15:30:42 +0200 |
| commit | fcce9f14f07db15650d84650293e2207f7dabbfa (patch) | |
| tree | 362bbc0495f56ba9604dd93dc0d016eeb7515119 /drivers/gpio/gpio-merrifield.c | |
| parent | gpio: merrifield: Introduce GPIO driver to support Merrifield (diff) | |
| download | linux-fcce9f14f07db15650d84650293e2207f7dabbfa.tar.xz linux-fcce9f14f07db15650d84650293e2207f7dabbfa.zip | |
gpio: merrifield: Protect irq_ack() and gpio_set() by lock
There is a potential race when two threads do the writes to the same register
in parallel.
Prevent out of order in such case by protecting I/O access by spin lock.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'drivers/gpio/gpio-merrifield.c')
| -rw-r--r-- | drivers/gpio/gpio-merrifield.c | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/drivers/gpio/gpio-merrifield.c b/drivers/gpio/gpio-merrifield.c index 11066f6eb412..45b51278b8ee 100644 --- a/drivers/gpio/gpio-merrifield.c +++ b/drivers/gpio/gpio-merrifield.c @@ -105,7 +105,11 @@ static int mrfld_gpio_get(struct gpio_chip *chip, unsigned int offset) static void mrfld_gpio_set(struct gpio_chip *chip, unsigned int offset, int value) { + struct mrfld_gpio *priv = gpiochip_get_data(chip); void __iomem *gpsr, *gpcr; + unsigned long flags; + + raw_spin_lock_irqsave(&priv->lock, flags); if (value) { gpsr = gpio_reg(chip, offset, GPSR); @@ -114,6 +118,8 @@ static void mrfld_gpio_set(struct gpio_chip *chip, unsigned int offset, gpcr = gpio_reg(chip, offset, GPCR); writel(BIT(offset % 32), gpcr); } + + raw_spin_unlock_irqrestore(&priv->lock, flags); } static int mrfld_gpio_direction_input(struct gpio_chip *chip, @@ -160,8 +166,13 @@ static void mrfld_irq_ack(struct irq_data *d) struct mrfld_gpio *priv = irq_data_get_irq_chip_data(d); u32 gpio = irqd_to_hwirq(d); void __iomem *gisr = gpio_reg(&priv->chip, gpio, GISR); + unsigned long flags; + + raw_spin_lock_irqsave(&priv->lock, flags); writel(BIT(gpio % 32), gisr); + + raw_spin_unlock_irqrestore(&priv->lock, flags); } static void mrfld_irq_unmask_mask(struct irq_data *d, bool unmask) |