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authorChris Wilson <chris@chris-wilson.co.uk>2011-01-08 10:02:21 +0100
committerChris Wilson <chris@chris-wilson.co.uk>2011-01-11 21:44:54 +0100
commitdb66e37d239b45f36a3f6495cf4ec49391b2c089 (patch)
treed16899c361fb77e7732eb603835cb95c3af49421 /drivers/gpu/Makefile
parentdrm/i915: Propagate error from flushing the ring (diff)
downloadlinux-db66e37d239b45f36a3f6495cf4ec49391b2c089.tar.xz
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drm/i915: Include TLB miss overhead for computing WM
The docs recommend that if 8 display lines fit inside the FIFO buffer, then the number of watermark entries should be increased to hide the latency of filling the rest of the FIFO buffer. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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