diff options
| author | Dennis Li <Dennis.Li@amd.com> | 2021-01-27 07:36:15 +0100 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2021-03-24 03:59:50 +0100 |
| commit | 4abc2567f0ebf1c7113430e25ee960408f5ebcb1 (patch) | |
| tree | 520688e97b23d4d72af01f56159498d8b54a701e /drivers/gpu/drm/amd/amdgpu/soc15.h | |
| parent | drm/amdgpu: add ras support for gfx of aldebaran (diff) | |
| download | linux-4abc2567f0ebf1c7113430e25ee960408f5ebcb1.tar.xz linux-4abc2567f0ebf1c7113430e25ee960408f5ebcb1.zip | |
drm/amdgpu: refine ras codes for GC utc of aldebaran
The bank number of both VML2 and ATCL2 are changed to 8, so refine
related codes to avoid defining long name arrays.
Signed-off-by: Dennis Li <Dennis.Li@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/soc15.h')
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/soc15.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.h b/drivers/gpu/drm/amd/amdgpu/soc15.h index ea0469e45b9f..034cfdfc4dbe 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc15.h +++ b/drivers/gpu/drm/amd/amdgpu/soc15.h @@ -97,7 +97,7 @@ struct soc15_ras_field_entry { #define SOC15_REG_FIELD_VAL(val, mask, shift) (((val) & mask) >> shift) -#define SOC15_RAS_REG_FIELD_VAL(val, entry, field) SOC15_REG_FIELD_VAL(val, entry.field##_count_mask, entry.field##_count_shift) +#define SOC15_RAS_REG_FIELD_VAL(val, entry, field) SOC15_REG_FIELD_VAL((val), (entry).field##_count_mask, (entry).field##_count_shift) void soc15_grbm_select(struct amdgpu_device *adev, u32 me, u32 pipe, u32 queue, u32 vmid); |