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| author | Charlene Liu <charlene.liu@amd.com> | 2019-04-30 19:01:12 +0200 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2019-06-22 16:34:11 +0200 |
| commit | bb21290ff61529f7b8a6acdba6bbc21b15ac8c18 (patch) | |
| tree | 5297b0bc1316ec83614388a29ed5bce8cc178314 /drivers/gpu/drm/amd/include | |
| parent | drm/amd/display: Intermittent DCN2 pipe hang on mode change (diff) | |
| download | linux-bb21290ff61529f7b8a6acdba6bbc21b15ac8c18.tar.xz linux-bb21290ff61529f7b8a6acdba6bbc21b15ac8c18.zip | |
drm/amd/display: Create DWB resource for DCN2
[Description]
dcn20 has num_dwb =1 in the res cap, but not created.
Signed-off-by: Charlene Liu <charlene.liu@amd.com>
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Duke Du <Duke.Du@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/include')
| -rw-r--r-- | drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h | 4 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_sh_mask.h | 16 |
2 files changed, 20 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h index e3188516cfbf..cff8f91555d3 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h +++ b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h @@ -889,6 +889,8 @@ #define mmCNV_TEST_CRC_BLUE_BASE_IDX 2 #define mmWB_DEBUG_CTRL 0x01f2 #define mmWB_DEBUG_CTRL_BASE_IDX 2 +#define mmWB_DBG_MODE 0x01f3 +#define mmWB_DBG_MODE_BASE_IDX 2 #define mmWB_HW_DEBUG 0x01f4 #define mmWB_HW_DEBUG_BASE_IDX 2 #define mmWB_SOFT_RESET 0x01f5 @@ -1065,6 +1067,8 @@ #define mmMCIF_WB0_MCIF_WB_SELF_REFRESH_CONTROL_BASE_IDX 2 #define mmMCIF_WB0_MULTI_LEVEL_QOS_CTRL 0x02d9 #define mmMCIF_WB0_MULTI_LEVEL_QOS_CTRL_BASE_IDX 2 +#define mmMCIF_WB0_MCIF_WB_SECURITY_LEVEL 0x02da +#define mmMCIF_WB0_MCIF_WB_SECURITY_LEVEL_BASE_IDX 2 #define mmMCIF_WB0_MCIF_WB_BUF_LUMA_SIZE 0x02db #define mmMCIF_WB0_MCIF_WB_BUF_LUMA_SIZE_BASE_IDX 2 #define mmMCIF_WB0_MCIF_WB_BUF_CHROMA_SIZE 0x02dc diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_sh_mask.h index 5e78f741c053..10c83fecd147 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_sh_mask.h +++ b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_sh_mask.h @@ -5999,6 +5999,19 @@ #define WB_DEBUG_CTRL__WB_DEBUG_SEL__SHIFT 0x6 #define WB_DEBUG_CTRL__WB_DEBUG_EN_MASK 0x00000001L #define WB_DEBUG_CTRL__WB_DEBUG_SEL_MASK 0x000000C0L +//WB_DBG_MODE +#define WB_DBG_MODE__WB_DBG_MODE_EN__SHIFT 0x0 +#define WB_DBG_MODE__WB_DBG_DIN_FMT__SHIFT 0x1 +#define WB_DBG_MODE__WB_DBG_36MODE__SHIFT 0x2 +#define WB_DBG_MODE__WB_DBG_CMAP__SHIFT 0x3 +#define WB_DBG_MODE__WB_DBG_PXLRATE_ERROR__SHIFT 0x8 +#define WB_DBG_MODE__WB_DBG_SOURCE_WIDTH__SHIFT 0x10 +#define WB_DBG_MODE__WB_DBG_MODE_EN_MASK 0x00000001L +#define WB_DBG_MODE__WB_DBG_DIN_FMT_MASK 0x00000002L +#define WB_DBG_MODE__WB_DBG_36MODE_MASK 0x00000004L +#define WB_DBG_MODE__WB_DBG_CMAP_MASK 0x00000008L +#define WB_DBG_MODE__WB_DBG_PXLRATE_ERROR_MASK 0x00000100L +#define WB_DBG_MODE__WB_DBG_SOURCE_WIDTH_MASK 0x7FFF0000L //WB_HW_DEBUG #define WB_HW_DEBUG__WB_HW_DEBUG__SHIFT 0x0 #define WB_HW_DEBUG__WB_HW_DEBUG_MASK 0xFFFFFFFFL @@ -6646,6 +6659,9 @@ //MCIF_WB0_MULTI_LEVEL_QOS_CTRL #define MCIF_WB0_MULTI_LEVEL_QOS_CTRL__MAX_SCALED_TIME_TO_URGENT__SHIFT 0x0 #define MCIF_WB0_MULTI_LEVEL_QOS_CTRL__MAX_SCALED_TIME_TO_URGENT_MASK 0x003FFFFFL +//MCIF_WB0_MCIF_WB_SECURITY_LEVEL +#define MCIF_WB0_MCIF_WB_SECURITY_LEVEL__MCIF_WB_SECURITY_LEVEL__SHIFT 0x0 +#define MCIF_WB0_MCIF_WB_SECURITY_LEVEL__MCIF_WB_SECURITY_LEVEL_MASK 0x00000007L //MCIF_WB0_MCIF_WB_BUF_LUMA_SIZE #define MCIF_WB0_MCIF_WB_BUF_LUMA_SIZE__MCIF_WB_BUF_LUMA_SIZE__SHIFT 0x0 #define MCIF_WB0_MCIF_WB_BUF_LUMA_SIZE__MCIF_WB_BUF_LUMA_SIZE_MASK 0x000FFFFFL |