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author | Chris Wilson <chris@chris-wilson.co.uk> | 2016-04-29 14:18:22 +0200 |
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committer | Chris Wilson <chris@chris-wilson.co.uk> | 2016-04-29 14:59:05 +0200 |
commit | 0e4ca1008e101d781b430bfecae1ee6d945b7504 (patch) | |
tree | 1a39bf79dd08c610ba9b2bdd99b42998be8dccbd /drivers/gpu/drm/i915/i915_dma.c | |
parent | drm/i915: Apply strongly ordered RCS breadcrumb to gen8/legacy (diff) | |
download | linux-0e4ca1008e101d781b430bfecae1ee6d945b7504.tar.xz linux-0e4ca1008e101d781b430bfecae1ee6d945b7504.zip |
drm/i915: Fix ordering of sanitize ppgtt and sanitize execlists
The i915.enable_ppgtt option depends upon the state of
i915.enable_execlists option - so we need to sanitize execlists first.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1461932305-14637-2-git-send-email-chris@chris-wilson.co.uk
Diffstat (limited to 'drivers/gpu/drm/i915/i915_dma.c')
-rw-r--r-- | drivers/gpu/drm/i915/i915_dma.c | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c index f69330cf0118..c91387f1aedd 100644 --- a/drivers/gpu/drm/i915/i915_dma.c +++ b/drivers/gpu/drm/i915/i915_dma.c @@ -968,6 +968,19 @@ static void intel_device_info_runtime_init(struct drm_device *dev) info->has_subslice_pg ? "y" : "n"); DRM_DEBUG_DRIVER("has EU power gating: %s\n", info->has_eu_pg ? "y" : "n"); + + i915.enable_execlists = + intel_sanitize_enable_execlists(dev, i915.enable_execlists); + + /* + * i915.enable_ppgtt is read-only, so do an early pass to validate the + * user's requested state against the hardware/driver capabilities. We + * do this now so that we can print out any log messages once rather + * than every time we check intel_enable_ppgtt(). + */ + i915.enable_ppgtt = + intel_sanitize_enable_ppgtt(dev, i915.enable_ppgtt); + DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915.enable_ppgtt); } static void intel_init_dpio(struct drm_i915_private *dev_priv) |