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authorDaniel Vetter <daniel.vetter@ffwll.ch>2013-11-01 10:50:20 +0100
committerDaniel Vetter <daniel.vetter@ffwll.ch>2013-11-01 18:16:27 +0100
commit46a19188171179ba2d84e6de803ce7b1c54da474 (patch)
tree9d616d87c762c586ea7eabde04c827c331f9b196 /drivers/gpu/drm/i915/i915_drv.h
parentdrm/i915: use the correct register when turning VDD off (diff)
downloadlinux-46a19188171179ba2d84e6de803ce7b1c54da474.tar.xz
linux-46a19188171179ba2d84e6de803ce7b1c54da474.zip
drm/i916: add "auto" pipe CRC source
On gmch platforms the normal pipe source CRC registers don't work for DP and TV encoders. And on newer platforms the single pipe CRC has been replaced by a set of CRC at different stages in the platform. Now most of our userspace tests don't care one bit about the exact CRC, they simply want something that reflects any changes on the screen. Hence add a new auto target for platform agnostic tests to use. v2: Pass back the adjusted source so that it can be shown in debugfs. v3: I seem to be unable to get a stable CRC for DP ports. So let's just disable them for now when using the auto mode. Note that testcases need to be restructured so that they can dynamically skip connectors. They also first need to set up the desired mode configuration, since otherwise the auto mode won't do the right thing. v4: Don't leak the modeset mutex on error paths. v5: Spelling fix for the i9xx auto_source function. Cc: Damien Lespiau <damien.lespiau@intel.com> Reviewed-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_drv.h')
-rw-r--r--drivers/gpu/drm/i915/i915_drv.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 0a886fd24936..f2324bc46800 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1251,6 +1251,7 @@ enum intel_pipe_crc_source {
INTEL_PIPE_CRC_SOURCE_DP_B,
INTEL_PIPE_CRC_SOURCE_DP_C,
INTEL_PIPE_CRC_SOURCE_DP_D,
+ INTEL_PIPE_CRC_SOURCE_AUTO,
INTEL_PIPE_CRC_SOURCE_MAX,
};