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authorImre Deak <imre.deak@intel.com>2020-02-28 16:33:28 +0100
committerImre Deak <imre.deak@intel.com>2020-03-02 18:36:22 +0100
commitccc495fd7ac3815702378712bccc1cbfc7852b58 (patch)
treea1faa650c4512160fb3af42f3303281aa5a4b2ea /drivers/gpu/drm/i915/i915_drv.h
parentdrm/i915/hsw: Use the read-out WRPLL/SPLL state instead of reading out again (diff)
downloadlinux-ccc495fd7ac3815702378712bccc1cbfc7852b58.tar.xz
linux-ccc495fd7ac3815702378712bccc1cbfc7852b58.zip
drm/i915: Unify the DPLL ref clock frequency tracking
All platforms using the shared DPLL framework use 3 reference clocks for their DPLLs: SSC, non-SSC and DSI. For a more unified way across platforms store the frequency of these ref clocks as part of the DPLL global state. This also allows us to keep the HW access reading out the ref clock value separate from the DPLL frequency calculation that depends on the ref clock. For now add only the SSC and non-SSC ref clocks, as the pre-ICL DSI code has its own logic for calculating DPLL parameters instead of the shared DPLL framework. v2: - Apply the ICL combo PHY PLL ref_clock/2 adjustment during the frequency->PLL param conversion direction as well. (CI shards) - s/kHZ/kHz/ (Ville) Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200228153328.17842-1-imre.deak@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/i915_drv.h')
-rw-r--r--drivers/gpu/drm/i915/i915_drv.h5
1 files changed, 5 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 43a47b7deaa0..b5134ff66f03 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1029,6 +1029,11 @@ struct drm_i915_private {
int num_shared_dpll;
struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
const struct intel_dpll_mgr *mgr;
+
+ struct {
+ int nssc;
+ int ssc;
+ } ref_clks;
} dpll;
struct list_head global_obj_list;