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authorEric Anholt <eric@anholt.net>2009-11-02 21:08:22 +0100
committerEric Anholt <eric@anholt.net>2010-02-26 22:23:18 +0100
commitf6e450a6417460db6a74241de8aaab5116cac140 (patch)
treef86f3f3faffe0ac9d6485b46c440ca7fc62bdd54 /drivers/gpu/drm/i915/i915_gem.c
parentdrm/i915: Set up fence registers on sandybridge. (diff)
downloadlinux-f6e450a6417460db6a74241de8aaab5116cac140.tar.xz
linux-f6e450a6417460db6a74241de8aaab5116cac140.zip
drm/i915: Fix sandybridge status page setup.
The register's moved to the same location as the one for the BCS, it seems. Signed-off-by: Eric Anholt <eric@anholt.net>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_gem.c')
-rw-r--r--drivers/gpu/drm/i915/i915_gem.c9
1 files changed, 7 insertions, 2 deletions
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 715eaac62dbd..c73da4049c81 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -4581,8 +4581,13 @@ i915_gem_init_hws(struct drm_device *dev)
}
dev_priv->hws_obj = obj;
memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
- I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr);
- I915_READ(HWS_PGA); /* posting read */
+ if (IS_GEN6(dev)) {
+ I915_WRITE(HWS_PGA_GEN6, dev_priv->status_gfx_addr);
+ I915_READ(HWS_PGA_GEN6); /* posting read */
+ } else {
+ I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr);
+ I915_READ(HWS_PGA); /* posting read */
+ }
DRM_DEBUG_DRIVER("hws offset: 0x%08x\n", dev_priv->status_gfx_addr);
return 0;