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author | Michel Thierry <michel.thierry@intel.com> | 2018-06-05 01:32:49 +0200 |
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committer | Lionel Landwerlin <lionel.g.landwerlin@intel.com> | 2018-06-11 12:58:13 +0200 |
commit | 9904b1560e4a2e7c956004f9843939e23d84cd7b (patch) | |
tree | e77df8daa7df3962789c74b2b8d5dc9e6785ee01 /drivers/gpu/drm/i915/i915_perf.c | |
parent | drm/i915: Apply batch location restrictions before pinning (diff) | |
download | linux-9904b1560e4a2e7c956004f9843939e23d84cd7b.tar.xz linux-9904b1560e4a2e7c956004f9843939e23d84cd7b.zip |
drm/i915/perf: use the lrc_desc to get the ctx hw id in gen8-10
The upper 32 bits of the lrc_desc (bits 52-32 to be precise) are the
context hw id in GEN8-10, so use them and have one less thing to
maintain in the unlikely case we change the descriptor sw fields.
v2: If we use the lrc_desc, we must apply the ctx_id_mask too (Lionel)
Signed-off-by: Michel Thierry <michel.thierry@intel.com>
Cc: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180604233250.609-1-michel.thierry@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/i915_perf.c')
-rw-r--r-- | drivers/gpu/drm/i915/i915_perf.c | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c index a6c8d61add0c..6aba30cb40ea 100644 --- a/drivers/gpu/drm/i915/i915_perf.c +++ b/drivers/gpu/drm/i915/i915_perf.c @@ -1279,9 +1279,12 @@ static int oa_get_render_ctx_id(struct i915_perf_stream *stream) i915->perf.oa.specific_ctx_id_mask = (1U << (GEN8_CTX_ID_WIDTH - 1)) - 1; } else { - i915->perf.oa.specific_ctx_id = stream->ctx->hw_id; i915->perf.oa.specific_ctx_id_mask = (1U << GEN8_CTX_ID_WIDTH) - 1; + i915->perf.oa.specific_ctx_id = + upper_32_bits(ce->lrc_desc); + i915->perf.oa.specific_ctx_id &= + i915->perf.oa.specific_ctx_id_mask; } break; |