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| author | Eugeni Dodonov <eugeni.dodonov@intel.com> | 2012-04-13 22:08:38 +0200 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2012-04-17 11:50:49 +0200 |
| commit | ef4d084fae9d4719bc52f97e15e41e1602e3bc6e (patch) | |
| tree | c6cf0c06ac87d2ce59c4e2a688fea723b631eff8 /drivers/gpu/drm/i915/i915_reg.h | |
| parent | drm/i915: add definition of LPT FDI port width registers (diff) | |
| download | linux-ef4d084fae9d4719bc52f97e15e41e1602e3bc6e.tar.xz linux-ef4d084fae9d4719bc52f97e15e41e1602e3bc6e.zip | |
drm/i915: add WRPLL divider programming bits
Those are used to program the WRPLL dividers correctly for each gives
frequency.
Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index bc1a5c60822e..0668815d05d7 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -4191,6 +4191,10 @@ #define WRPLL_PLL_SELECT_SSC (0x01<<28) #define WRPLL_PLL_SELECT_NON_SCC (0x02<<28) #define WRPLL_PLL_SELECT_LCPLL_2700 (0x03<<28) +/* WRPLL divider programming */ +#define WRPLL_DIVIDER_REFERENCE(x) ((x)<<0) +#define WRPLL_DIVIDER_POST(x) ((x)<<8) +#define WRPLL_DIVIDER_FEEDBACK(x) ((x)<<16) /* Port clock selection */ #define PORT_CLK_SEL_A 0x46100 |