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| author | Paulo Zanoni <paulo.r.zanoni@intel.com> | 2012-12-01 15:04:25 +0100 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2012-12-10 11:14:29 +0100 |
| commit | dde86e2db54545ef981b64805097a7b4c3156d6e (patch) | |
| tree | 636b940145e9bc2fd434a7bc35b210eba73c33cb /drivers/gpu/drm/i915/intel_crt.c | |
| parent | drm/i915: add support for mPHY destination on intel_sbi_{read, write} (diff) | |
| download | linux-dde86e2db54545ef981b64805097a7b4c3156d6e.tar.xz linux-dde86e2db54545ef981b64805097a7b4c3156d6e.zip | |
drm/i915: add lpt_init_pch_refclk
We need this code to init the PCH SSC refclk and the FDI registers.
The BIOS does this too and that's why VGA worked before this patch,
until you tried to suspend the machine...
This patch implements the "Sequence to enable CLKOUT_DP for FDI usage
and configure PCH FDI/IO" from our documentation.
v2:
- Squash Damien Lespiau's reset spelling fix on top.
- Add a comment that we don't need to bother about the ULT special
case Damien noticed, since ULT won't have VGA.
- Add a comment to rip out the SDV codepaths once haswell ships for
real.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> (v1)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_crt.c')
0 files changed, 0 insertions, 0 deletions