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author | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2018-04-03 23:24:18 +0200 |
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committer | Rodrigo Vivi <rodrigo.vivi@intel.com> | 2018-04-20 23:28:15 +0200 |
commit | e04f7ece1c4530b4f0db182b5596fadf48628f22 (patch) | |
tree | cded2ab405c72ed7cc747c19d78a9aa59a319049 /drivers/gpu/drm/i915/intel_display.h | |
parent | drm/i915: Enable edp psr error interrupts on hsw (diff) | |
download | linux-e04f7ece1c4530b4f0db182b5596fadf48628f22.tar.xz linux-e04f7ece1c4530b4f0db182b5596fadf48628f22.zip |
drm/i915: Enable edp psr error interrupts on bdw+
Plug in the bdw+ irq handling for PSR interrupts. bdw+ supports psr on
any transcoder in theory, though the we don't currenty enable PSR except
on the EDP transcoder.
v2: From DK
* Rebased on drm-tip
v3: Switched author to Ville based on IRC discussion.
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Reviewed-by: Jose Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180403212420.25007-2-dhinakaran.pandiyan@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/intel_display.h')
-rw-r--r-- | drivers/gpu/drm/i915/intel_display.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.h b/drivers/gpu/drm/i915/intel_display.h index 4e7418b345bc..2ef31617614a 100644 --- a/drivers/gpu/drm/i915/intel_display.h +++ b/drivers/gpu/drm/i915/intel_display.h @@ -218,6 +218,10 @@ struct intel_link_m_n { for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++) \ for_each_if((__mask) & BIT(__p)) +#define for_each_cpu_transcoder_masked(__dev_priv, __t, __mask) \ + for ((__t) = 0; (__t) < I915_MAX_TRANSCODERS; (__t)++) \ + for_each_if ((__mask) & (1 << (__t))) + #define for_each_universal_plane(__dev_priv, __pipe, __p) \ for ((__p) = 0; \ (__p) < INTEL_INFO(__dev_priv)->num_sprites[(__pipe)] + 1; \ |